{"id":416995,"date":"2024-10-20T06:13:47","date_gmt":"2024-10-20T06:13:47","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/bs-en-60749-292011-2\/"},"modified":"2024-10-26T11:34:51","modified_gmt":"2024-10-26T11:34:51","slug":"bs-en-60749-292011-2","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/bsi\/bs-en-60749-292011-2\/","title":{"rendered":"BS EN 60749-29:2011"},"content":{"rendered":"
This part of IEC 60749 covers the I-test and the overvoltage latch-up testing of integrated circuits.<\/p>\n
This test is classified as destructive.<\/p>\n
The purpose of this test is to establish a method for determining integrated circuit (IC) latch-up characteristics and to define latch-up failure criteria. Latch-up characteristics are used in determining product reliability and minimizing “no trouble found” (NTF) and “electrical overstress” (EOS) failures due to latch-up.<\/p>\n
This test method is primarily applicable to CMOS devices. Applicability to other technologies must be established.<\/p>\n
The classification of latch-up as a function of temperature is defined in 3.1 and the failure level criteria are defined in 3.2<\/p>\n
PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
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5<\/td>\n | English \n CONTENTS <\/td>\n<\/tr>\n | ||||||
6<\/td>\n | 1 Scope and object 2 Terms and definitions <\/td>\n<\/tr>\n | ||||||
9<\/td>\n | 3 Classification and levels 3.1 Classification 3.2 Levels 4 Apparatus and material 4.1 Latch-up tester <\/td>\n<\/tr>\n | ||||||
10<\/td>\n | Figures \n Figure 1 \u2013 Vsupply qualification circuit <\/td>\n<\/tr>\n | ||||||
12<\/td>\n | Figure 3 \u2013 Latch-up test flow <\/td>\n<\/tr>\n | ||||||
13<\/td>\n | Tables \n Table 1 \u2013 Test matrixa <\/td>\n<\/tr>\n | ||||||
14<\/td>\n | 5.2 Detailed latch-up test procedure Table 2 \u2013 Timing specifications for I-test and Vsupply overvoltage test <\/td>\n<\/tr>\n | ||||||
21<\/td>\n | 6 Failure criteria 7 Summary <\/td>\n<\/tr>\n | ||||||
22<\/td>\n | Annex A (informative) \nExamples of special pins that are connectedto passive components <\/td>\n<\/tr>\n | ||||||
23<\/td>\n | Figure A.1 \u2013 Examples of special pins that are connected to passive components <\/td>\n<\/tr>\n | ||||||
24<\/td>\n | Annex B (informative) Calculation of operating ambient or operating case temperature \nfor a given operating junction temperature <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" Semiconductor devices. Mechanical and climatic test methods – Latch-up test<\/b><\/p>\n |