BS EN 61523-2:2002

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Delay and power calculation standards – Pre-layout delay calculation specification for CMOS ASIC libraries

Published By	Publication Date	Number of Pages
BSI	2002	42

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Categories: 35.240.50 - IT applications in industry, BSI

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Description

Applies to CMOS ASIC libraries which contain cell based primitives and memories to be used during the pre-layout design phase of logic simulation, timing verification and logic synthesis.The delay calculation method addressed in this standard consists of 1) estimation of wire capacitance 2 ) Delay calculation method based on tablelook-up. With use of DCL and SDF, this delay calculation method helps the user have a unified timing model for various EDA tools in the pre-layout design phase.

Additional information

Status	Withdrawn
Pages	42
Publication Date	2002-09-27
Withdrawn Date	2014-08-31
ISBN	0 580 40460 9
Standard Number	BS EN 61523-2:2002
Title	Delay and power calculation standards – Pre-layout delay calculation specification for CMOS ASIC libraries
Identical National Standard Of	EN 61523-2 (IEC 61523-2:2002) AS, IEC 61523-2:2002
Descriptors	Metal oxide semiconductors, Electronic engineering, Semiconductors, Integrated circuits, Computerized control
Publisher	BSI
Committee	EPL/501
ICS Codes	35.240.50 - IT applications in industry

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BS EN 61523-2:2002

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