BS IEC 62530:2007

$215.11

Standard for SystemVerilog. Unified hardware design, specification and verification language

Published By	Publication Date	Number of Pages
BSI	2007	664

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Categories: 25.040.01 - Industrial automation systems in general, BSI

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Description

Specifies extensions for a higher level of abstraction for modeling and verification with the Verilog hardware description language (HDL). This standard includes design specification methods, embedded assertions language, testbench language including coverage and assertions application programming interface (API), and a direct programming interface (DPI)>

Additional information

Status	Withdrawn
Title	Standard for SystemVerilog. Unified hardware design, specification and verification language
Publisher	BSI
Committee	EPL/501
Pages	664
Publication Date	2007-12-31
Withdrawn Date	2011-07-31
Replaced By	BS IEC 62530:2011
ISBN	978 0 580 59320 8
Standard Number	BS IEC 62530:2007
Identical National Standard Of	IEC 62530:2011, IEC 60950-23:2005, IEC 62530:2007
Descriptors	Computer programs, Electronic equipment and components, Interfaces (data processing), Syntax, Verification, Data processing, Data representation, Design, Computer hardware, Data, Programming languages, Semantics, Data transfer
ICS Codes	25.040.01 - Industrial automation systems in general

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BS IEC 62530:2007

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