BS IEC 63011-1:2018:2019 Edition

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Integrated circuits. Three dimensional integrated circuits – Terminology

Published By	Publication Date	Number of Pages
BSI	2019	16

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Description

IEC 63011-1:2018 provides definitions pertaining to multichip integrated circuits, as vertically stacked dies using through-silicon vias (TSVs) or micro bumps. Terms and definitions related to the fabrication and test of the multichip integrated circuits are also provided.

PDF Catalog

PDF Pages	PDF Title
2	undefined
4	English CONTENTS
5	FOREWORD
7	INTRODUCTION
8	1 Scope 2 Normative reference 3 Terms and definitions 3.1 General
10	3.2 Test method in 3D environment
11	Figure 1 – Examples of TSVs
14	Bibliography

Additional information

Status	Definitive
Pages	16
Publication Date	2019-01-24
ISBN	978 0 580 96278 3
Standard Number	BS IEC 63011-1:2018
Title	Integrated circuits. Three dimensional integrated circuits – Terminology
Identical National Standard Of	IEC 63011-1:2018
Descriptors	Transient voltages, Integrated circuits, Semiconductors, Impulse voltages, Electronic equipment and components, Electromagnetic compatibility, Test equipment, Electrical measurement, Impulse-voltage tests
Publisher	BSI
Committee	EPL/47
ICS Codes	31.200 - Integrated circuits. Microelectronics

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BS IEC 63011-1:2018:2019 Edition

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