BSI PD IEC/TR 63094:2017
$142.49
Multimedia systems and equipment. Multimedia signal transmission. Dependable line code with error correction
| Published By | Publication Date | Number of Pages |
| BSI | 2017 | 26 |
This document specifies the line code 4b/10b for dependable multimedia signal transmission required for complex machines, such as robots and automobiles. This document corresponds to the functions specified in layer 1 to layer 2 of the OSI reference model (ISO/IEC 7498).
The purpose of this document is to facilitate the development and use of the 4b/10b in dependable systems by providing a line code protocol. This document provides a line code protocol for interconnections among distributed real-time systems, including embedded systems, control systems, amusement systems, robot systems, and intelligent buildings. The 4b/10b can achieve the line code with ECC (error code correction). The 4b/10b is the line code that realizes embedded clock, DC balance, error detection and error correction at a time; it is not possible to satisfy these functions in one codec by conventional schemes, and the 4b/10b line code can achieve highly reliable and dependable digital communications.
PDF Catalog
| PDF Pages | PDF Title |
|---|---|
| 2 | National foreword |
| 6 | CONTENTS |
| 7 | FOREWORD |
| 9 | INTRODUCTION |
| 10 | Figure 1 – A humanoid robot |
| 12 | 1 Scope 2 Normative references 3 Terms, definitions and abbreviated terms 3.1 Terms and definitions |
| 13 | 3.2 Abbreviated terms 4 4b/10b line code 4.1 Overview 4.2 Forward error correction (FEC) 4.3 Embedded clock 4.4 DC balance |
| 14 | 4.5 4b/10b data encoding 4.6 Frame format 4.6.1 Frame 4.6.2 Setup command Tables Table 1 – The 4b/10b data transform Table 2 – Setup command |
| 15 | 4.6.3 Idle command 4.7 Encoding 4.8 Decoding 4.9 Error handling 4.9.1 1-bit error Table 3 – Idle command Table 4 – The 4b/10b look-up |
| 16 | 4.9.2 2-bit error 4.9.3 Over 3-bit error |
| 17 | Annex A (informative) Real-time scheduling Figure A.1 – EDF scheduling |
| 18 | Annex B (informative) Characteristics of embedded clock Table B.1 – The length of successive 0 or 1 in case of 1-bit error |
| 19 | Annex C (informative) Characteristics of DC balance Table C.1 – An example of the isomery of 0 and 1 in a successive 10-bit window |
| 20 | Annex D (informative) Implementation of a decoder |
| 21 | Bibliography |
