BS IEC 62142:2005
$215.11
Standard for Verilog register transfer level synthesis
| Published By | Publication Date | Number of Pages |
| BSI | 2005 | 112 |
Defines a set of modeling rules for writing Verilog® HDL descriptions for synthesis. Adherence to these rules guarantees the interoperability of Verilog HDL descriptions between register-transfer level synthesis tools that comply to this standard. The standard de.nes how the semantics of Verilog HDL are used, for example, to describe level- and edge-sensitive logic. It also describes the syntax of the language with reference to what shall be supported and what shall not be supported for interoperability.
