BS ISO/IEC 10861:1994:1995 Edition
$215.11
Information technology. Microprocessor systems. High-performance synchronous 32-bit bus: MULTIBUS II
Published By | Publication Date | Number of Pages |
BSI | 1995 | 136 |
This International Standard defines the operation, functions, and attributes of the IEEE 1296 bus standard.
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This standard defines a high-performance 32-bit synchronous bus standard.
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The bus standard must have a design-in lifetime of 10 years with backward compatibility.
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The standard is intended for general purpose applications to optimize block transfers, including protocol for message passing. For real-time applications, the bus will provide a means of ensuring an upper limit to message delivery time.
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The standard is intended to be compatible with existing IEC mechanical standards (IEC Pub 297-1,1 297-3, and 603-2) with recognition of the need for special front panels to address ESD, EMI, and RFI requirements.
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Options within the standard will be clearly identified.
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The standard is intended to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system.
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The standard is intended to support heterogeneous processor types in the same system.
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Message-passing format and protocol is intended for future migration to a serial system bus.