This part of IEC 62240, which is a technical report, provides information when using semiconductor devices in wider temperature ranges than those specified by the device manufacturer. The uprating solutions described herein are considered exceptions, when no reasonable alternatives are available; otherwise devices are utilized within the manufacturers’ specifications.

The terms “uprating” and “thermal uprating” are being used increasingly in avionics industry discussions and meetings, and clear definitions are included in Clause 3. They were coined as shorthand references to a special case of methods commonly used in selecting electronic components for circuit design.

This document describes the methods and processes for implementing this special case of thermal uprating. All of the elements of these methods and processes employ existing, commonly used best engineering practices. No new or unique engineering knowledge is needed to follow these processes, only a rigorous application of the overall approach.

Even though the device is used at wider temperatures, the wider temperatures usage will be limited to those that do not compromise applications performance and reliability, particularly for devices with narrow feature size geometries (for example, 90 nm and less). This document does not imply that applications use the device to function beyond the absolute maximum rating limits specified by the original device manufacturer and assumes that:

device usage outside the original device manufacturers’ specified temperature ranges is done only when no reasonable alternative approach is available and is performed with appropriate justification;
if it is necessary to use devices outside the original device manufacturers’ specified temperature ranges, it is done with documented and controlled processes that assure integrity of the electronic equipment.

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PDF Pages	PDF Title
2	undefined
4	CONTENTS
7	FOREWORD
9	INTRODUCTION
10	1 Scope 2 Normative references 3 Terms, definitions and abbreviated terms 3.1 Terms and definitions
14	3.2 Abbreviated terms 4 Selection provisions 4.1 General
15	Figures Figure 1 – Flow chart for semiconductor devices over wider temperature ranges
16	4.2 Device selection, usage and alternatives 4.2.1 General 4.2.2 Alternatives 4.2.3 Device technology
17	4.2.4 Compliance with the electronic component management plan 4.3 Device capability assessment 4.3.1 General 4.3.2 Device package and internal construction capability assessment 4.3.3 Risk assessment (assembly level)
18	4.3.4 Device uprating methods
19	4.3.5 Device reliability assurance
20	4.4 Device quality assurance (QA) over wider temperature ranges 4.4.1 Decision for the optimum QA method
21	4.4.2 Device level testing 4.4.3 Higher level assembly testing 4.5.1 General 4.5.2 Semiconductor device change monitoring
22	4.6 Final electronic equipment assurance 4.7 Documentation and identification 4.7.1 Documentation 4.7.2 Device identification 4.7.3 Customer notification
23	Figure 2 – Report form for documenting device usage over wider temperature ranges
24	Annexes Annex A (informative) Device parameter re-characterisation A.1 Glossary of symbols
25	A.2 Rationale for parameter re-characterisation A.2.1 General A.2.2 Assessment for uprateability Figure A.1 – Parameter re-characterisation
26	A.3 Capability assurance A.3.1 Description A.3.2 Parameter re-characterisation process
27	Figure A.2 – Flow diagram of parameter re-characterisation capability assurance process
28	Tables Table A.1 – Example of sample size calculation
30	Figure A.3 – Margin in electrical parameter measurement based on the results of the sample test
31	A.3.3 Application capability assessment Figure A.4 – Schematic diagram of parameter limit modifications Table A.2 – Parameter re-characterisation example: SN74ALS244 octal buffer/driver
32	A.4 Quality assurance A.5 Factors to be considered in parameter re-characterisation Figure A.5 – Parameter re-characterisation device quality assurance
33	Figure A.6 – Schematic of outlier products that can invalidate sample testing
34	A.6 Report form for documenting device parameter re-characterisation Figure A.7 – Example of intermediate peak of an electrical parameter: Voltage feedback input threshold change for Motorola MC34261 power factor controller, see [4]
35	Figure A.8 – Report form for documenting device parameter re-characterisation
36	Annex B (informative) Stress balancing B.1 General B.2 Glossary of symbols B.3 Stress balancing B.3.1 General
37	B.3.2 Determine the ambient temperature extremes B.3.3 Determine parameter relationship to power dissipation B.3.4 Determine the dissipated power versus ambient temperature relationship
38	Figure B.1 – Iso-TJ curve: Relationship between ambient temperature and dissipated power
39	B.3.5 Assess applicability of the method B.3.6 Determine the new parameter values
40	B.3.7 Conduct parametric and functional tests B.4 Application example B.4.1 General Figure B.2 – Graph of electrical parameters versus dissipated power
41	B.4.2 Determine the ambient temperature extremes B.4.3 Select the parameters that can be derated
42	B.4.4 Construct an Iso-TJ plot B.4.5 Determine whether or not the device can be uprated B.4.6 Determine the new parameter values Figure B.3 – Iso-TJ curve for the Fairchild MM74HC244
43	B.4.7 Conduct parametric and functional tests B.5 Other notes B.5.1 Margins B.5.2 Cautions and limitations Figure B.4 – Power versus frequency curve for the Fairchild MM74HC244
44	Figure B.5 – Flow chart for stress balancing
45	Figure B.6 – Report form for documenting stress balancing
46	Annex C (informative) Parameter conformance assessment C.1 General C.2 Test plan C.2.1 General C.2.2 Critical parameters C.2.3 Minimum allowable test margins
47	C.2.4 Test options Figure C.1 – Relationship of temperature ratings, requirements and margins
49	Figure C.2 – Typical fallout distribution versus Treq-max
50	C.2.5 Quality assurance
51	Figure C.3 – Parameter conformance assessment flow
52	Figure C.4 – Report form for documenting parameter conformance testing
53	Annex D (informative) Higher assembly level testing D.1 General D.2 Process D.2.1 General D.2.2 Analysis of assembly test definition D.2.3 Perform assembly test
54	D.2.4 Document results D.2.5 Maintenance notification Figure D.1 – Flow chart of higher level assembly testing
55	Figure D.2 – Report form for documenting higherlevel assembly test at temperature extremes
56	Bibliography

Published By	Publication Date	Number of Pages
BSI	2018	58


PDF Format	Searchable	Printable	Preview Now

Status	Definitive
Pages	58
Publication Date	2018-04-11
ISBN	978 0 580 51225 4
Standard Number	PD IEC/TR 62240-1:2018
Title	Process management for avionics. Electronic components capability in operation – Temperature uprating
Identical National Standard Of	IEC TR 62240-1:2018
Replaces	PD IEC/TR 62240-1:2013
Descriptors	Performance, Operating conditions, Semiconductor devices, Integrated circuits, Semiconductors, Electronic equipment and components, Overheating, Temperature
Publisher	BSI
Committee	GEL/107
ICS Codes	31.020 - Electronic components in general

BSI PD IEC/TR 62240-1:2018

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