IEEE 1394a 2000

$72.04

IEEE Standard for a High Performance Serial Bus (Amendment)

Published By	Publication Date	Number of Pages
IEEE	2000	204

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Description

– Inactive – Superseded. Amended information for a high-speed Serial Bus that integrates well with most IEEE stan-dard 32-bit and 64-bit parallel buses is specified. This amendment is intended to extend the usefulness of a low-cost interconnect between external peripherals, as described in IEEE Std 1394-1995. This amendment to IEEE Std 1394-1995 follows the ISO/IEC 13213:1994 Command and Status Register (CSR) Architecture.

PDF Catalog

PDF Pages	PDF Title
1	Title Page
3	Introduction
4	Patent Notice Participants
7	CONTENTS
9	0. Introduction 0.1 Scope
10	0.2 Purpose 0.3 Document organization
11	1. Overview 1.2 References
12	1.5 Service model
13	1.6 Document notation 1.6.1 Mechanical notation 1.6.2 Signal naming 1.6.3 Size notation
14	1.6.4 Numerical values 1.6.5 Packet formats
15	1.6.6 Register formats 1.6.7 C code notation
16	1.6.8 State machine notation 1.6.9 CSR, ROM, and field notation
17	1.6.10 Register specification format
18	1.6.11 Reserved CSR fields
19	2. Definitions and abbreviations 2.1 Conformance 2.2 Technical glossary
23	3. Summary description 3.9 New features of IEEE Std 1394a-2000 3.9.1 Connection debounce
24	3.9.2 Cable arbitration enhancements 3.9.2.1 Arbitrated (short) bus reset
25	3.9.2.2 Ack-accelerated arbitration
26	3.9.2.3 Fly-by concatenation 3.9.2.4 Multi-speed-packet concatenation
27	3.9.2.5 Arbitration enhancements and cycle start 3.9.3 Performance optimization via PHY “pinging”
28	3.9.4 Priority arbitration 3.9.5 Port disable, suspend, and resume
29	3.9.5.1 Connection detect circuit 3.9.5.2 Suspended connection
30	3.9.5.3 Suspended domain 3.9.5.4 Resumption
31	3.9.5.5 Boundary nodes
32	4. Cable PHY specification 4.2 Cable physical connection specification 4.2.1 Media attachment 4.2.1.4 Signal propagation performance 4.2.1.4.8 Shield ac coupling
33	4.2.1A Alternative cable media attachment specification 4.2.1A.1 Connectors 4.2.1A.1.1 Connector plug
34	4.2.1A.1.2 Connector plug terminations 4.2.1A.1.3 Connector socket
37	4.2.1A.1.4 Contact finish on plug and socket contacts 4.2.1A.1.5 Termination finish on plug and contact socket terminals 4.2.1A.1.6 Shell finish on plugs and sockets 4.2.1A.1.7 Connector durability
38	4.2.1A.1.8 Printed circuit board footprints 4.2.1A.2 Cables 4.2.1A.2.1 Cable material (informative)
39	4.2.1A.2.2 Cable assemblies
40	4.2.1A.3 Connector and cable assembly performance criteria
41	4.2.1A.3.1 Performance group A: Basic mechanical dimensional conformance and electrical functiona…
42	4.2.1A.3.2 Performance group B: Low-level contact resistance when subjected to thermal shock and …
43	4.2.1A.3.3 Performance group C: Insulator integrity when subjected to thermal shock and humidity …
44	4.2.1A.3.4 Performance group D: Contact life and durability when subjected to mechanical cycling …
45	4.2.1A.3.5 Performance group E: Contact resistance and unmating force when subjected to temperatu…
47	4.2.1A.3.6 Performance group F: Mechanical retention and durability 4.2.1A.3.7 Performance group G: General tests
49	4.2.1A.4 Signal propagation performance criteria 4.2.1A.4.1 Signal impedance 4.2.1A.4.2 Signal pairs attenuation 4.2.1A.4.3 Signal pairs propagation delay
50	4.2.1A.4.4 Signal pairs relative propagation skew 4.2.1A.4.5 Crosstalk 4.2.2 Media signal interface
51	4.2.2 Media signal interface 4.2.2 Port interface
53	4.2.2.7 Cable power and ground
55	4.2.3 Media signal timing 4.2.3.2 Data signal rise and fall times
56	4.3 Cable PHY facilities 4.3.3 Cable PHY line states 4.3.4 Cable PHY packets
57	4.3.4.1 Self-ID packets
59	4.3.4.2 Link-on packet 4.3.4.3 PHY configuration packet
60	4.3.4.4 Extended PHY packets 4.3.4.4.1 Ping packet
61	4.3.4.4.2 Remote access packet 4.3.4.4.3 Remote reply packet
62	4.3.4.4.4 Remote command packet
63	4.3.4.4.5 Remote confirmation packet 4.3.4.4.6 Resume packet
64	4.3.5 Cable PHY timing constants 4.3.5 Cable interface timing constants
68	4.3.6 Gap timing
69	4.3.8 Node variables
70	4.3.9 Port variables 4.4 Cable physical layer operation
74	4.4.1 Speed-signal sampling and filtering
76	4.4.2 Data transmission and reception 4.4.2.1 Data transmission
77	4.4.2.2 Data reception and repeat
80	4.4.3 Arbitration 4.4.3.1 Bus reset 4.4.3.1.1 Bus reset state machine notes
81	4.4.3.1.2 Bus reset actions and conditions
83	4.4.3.2 Tree identify 4.4.3.2.1 Tree ID state machine notes
85	4.4.3.2.2 Tree ID actions and conditions
86	4.4.3.3 Self-identify 4.4.3.3.1 Self-ID state machine notes
88	4.4.3.3.2 Self-ID actions and conditions
90	4.4.3.4 Normal arbitration 4.4.3.4.1 Normal arbitration state machine notes
93	4.4.3.4.2 Normal arbitration actions and conditions
95	4.4.3.4.3 Receive actions and conditions
96	4.4.3.4.4 Transmit actions and conditions
97	4.4.3.4.5 PHY response actions and conditions
99	4.4.4 Port connection 4.4.4.1 Port connection state machine notes
102	4.4.4.2 Port connection actions and conditions
106	5A. PHY/link interface specification
133	5B. PHY register map
141	6. Link layer specification 6.1 Link layer services 6.1.1 Link layer bus management services for the node controller 6.1.1.3 Link event indication (LK_EVENT.indication) 6.1.2 Link layer asynchronous data services for the transaction layer 6.1.2.3 Link data indication (LK_DATA.indication)
142	6.1.3 Link layer isochronous data services for application layers 6.1.3.4 Link isochronous indication (LK_ISO.indication) 6.2 Link layer facilities 6.2.2 Asynchronous packets 6.2.2.2 Asynchronous packet formats with data block payload 6.2.2.2.3 Cycle start
143	6.2.2.3 Asynchronous packet formats with data block payload 6.2.2.3.3 Read response for data block 6.2.3 Isochronous packets 6.2.3.1 Isochronous data block packet format
144	6.2.3A Asynchronous stream packets
145	6.2.3A Asynchronous stream packets 6.2.3A.1 Asynchronous stream packet format 6.2.3A.2 Global asynchronous stream packet (GASP) format
146	6.2.3A.3 Loose vs. strict isochronous packet reception
147	6.2.4 Primary packet components 6.2.4.4 Retry code (rt) 6.2.4.5 Transaction codes (tcode)
148	6.2.4.12 Tag 6.2.4.12 Tag (isochronous stream packets) 6.2.5 Acknowledge packets 6.2.5.2 ACK packet components 6.2.5.2.2 Acknowledge codes (ack_code)
150	6.3 Link layer operation 6.3.1 Overview of link layer operation 6.3.1.1A Priority arbitration for PHY packets and response packets
151	7. Transaction layer specification 7.1 Transaction layer services 7.1.2 Transaction layer data services for applications and bus management 7.1.2.1 Transaction data request (TRAN_DATA.request) 7.1.2.4 Transaction data response (TRAN_DATA.response)
152	7.3 Transaction operation 7.3.1 Overview of transaction layer operations 7.3.1.3A Response codes (rcode) 7.3.1.3A.1 No response 7.3.1.3A.2 resp_complete 7.3.1.3A.3 resp_conflict_error
153	7.3.1.3A.4 resp_data_error 7.3.1.3A.5 resp_type_error 7.3.1.3A.6 resp_address_error
154	7.3.3 Details of transaction layer operation 7.3.3.1 Outbound transaction state machine 7.3.3.1.2 Sending a transaction request 7.3.3.1.3 Sending a transaction response 7.3.4 Transaction types 7.3.4.3 Lock transactions
155	7.3.5 Retry protocols
156	7.3.5.1 Outbound subaction retry protocol
157	7.3.5.2 Inbound subaction single-phase retry protocol 7.3.5.3 Inbound subaction dual-phase retry protocol
161	7.4 CSR Architecture transactions mapped to Serial Bus
162	8. Serial Bus management specification 8.2 Serial Bus management services 8.2.1 Serial Bus control request (SB_CONTROL.request) 8.2.3 Serial Bus event indication (SB_EVENT.indication) 8.3 Serial Bus management facilities 8.3.1 Node capabilities taxonomy
163	8.3.1.1 Repeater (cable environment) 8.3.1.2 Transaction capable 8.3.1.3 Isochronous capable 8.3.1.4 Cycle master capable
164	8.3.1.5 Isochronous resource manager capable 8.3.1.6 Bus manager capable (cable environment)
165	8.3.2 Command and status registers 8.3.2.2 CSR Architecture core registers 8.3.2.2.1 STATE_CLEAR register
166	8.3.2.2.3 NODE_IDS register
167	8.3.2.2.4 Command reset effects 8.3.2.2.6 SPLIT_TIMEOUT register
168	8.3.2.3 Serial-Bus-dependent registers
169	8.3.2.3.5A PRIORITY_BUDGET register
170	8.3.2.3.7 BANDWIDTH_AVAILABLE register
171	8.3.2.3.8 CHANNELS_AVAILABLE register
172	8.3.2.3.11 BROADCAST_CHANNEL register
173	8.3.2.4 Unit registers
174	8.3.2.4.2 SPEED_MAP registers (cable environment) 8.3.2.5 Configuration ROM 8.3.2.5.4 Configuration ROM Bus_Info_Block
177	8.4 Serial Bus management operations 8.4.2 Bus configuration procedures (cable environment) 8.4.2.3 Determination of the isochronous resource manager (cable environment)
178	8.4.2.5 Determination of the bus manager (cable environment) 8.4.2.6 Determination of the cycle master (cable environment) 8.4.2.6A Determination of the root (cable environment)
179	8.4.3 Isochronous management (cable environment) 8.4.3 Isochronous resource allocation (cable environment) 8.4.3.1 Bandwidth allocation
180	8.4.3.2 Channel allocation
181	8.4.5 Speed management (cable environment) 8.4.6 Topology management (cable environment) 8.4.6.2 Gap count optimization
182	8.5 Bus configuration state machines (cable environment) 8.5.4 Abdication by the bus manager
184	Annex A—Cable environment system properties
188	Annex C—Internal device physical interface
189	Annex C1—Transaction integrity safeguards
190	Annex E—Cable operation and implementation examples
194	Annex K—Serial Bus cable test procedures
201	Annex M—Serial Bus topology considerations for power distribution (cable environment)
204	Annex N—Bibliography