IEEE 1596 1992:2001 Edition

$109.96

IEEE Standard for Scalable Coherent Interface (SCI)

Published By	Publication Date	Number of Pages
IEEE	2001	255

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Description

New IEEE Standard – Active. The scalable coherent interface (SCI) provides computer-bus-like services but, instead of a bus, uses a collection of fast point-to-point unidirectional links to provide the far higher throughput needed for high-performance multiprocessor systems. SCI supports distributed, shared memory with optional cache coherence for tightly coupled systems, and message-passing for loosely coupled systems. Initial SCI links are defined at 1 Gbyte/s (16-bit parallel) and 1 Gb/s (serial). For applications requiring modular packaging, an interchangeable module is specified along with connector and power. The packets and protocols that implement transactions are defined and their formal specification is provided in the form of computer programs. In addition to the usual read-and-write transactions, SCI supports efficient multiprocessor lock transactions. The distributed cache-coherence protocols are efficient and can recover from an arbitrary number of transmission failures. SCI protocols ensure forward progress despite multiprocessor conflicts (no deadlocks or starvation).

PDF Catalog

PDF Pages	PDF Title
1	Title page
2	Copyright Page
5	Introduction
9	Participants
11	CONTENTS
13	1. Introduction 1.1 Document structure
14	1.2 SCI overview
20	1.3 Interconnect topologies
25	1.4 Transactions
42	1.5 Cache coherence
47	1.6 Reliability, availability, and support (RAS)
51	2. References, glossary, and notation 2.1 References 2.2 Conformance levels
52	2.3 Glossary
57	2.4 Bit and byte ordering
58	2.5 Numerical values
59	2.6 C code 3. Logical protocols and formats 3.1 Packet formats 3.2 Send and echo packet formats
77	3.3 Logical packet encodings
80	3.4 Transaction types
91	3.5 Elastic buffers
93	3.6 Bandwidth allocation
108	3.7 Queue allocation
112	3.8 Transaction errors
116	3.9 Transmission errors
122	3.10 Address initialization
133	3.11 Packet encoding
136	3.12 SCI-specific control and status registers
152	4. Cache-coherence protocols 4.1 Introduction
156	4.2 Coherence update sequences
163	4.3 Minimal-set coherence protocols
169	4.4 Typical-set coherence protocols
178	4.5 Full-set coherence protocols
193	4.6 C-code naming conventions
197	4.7 Coherent read and write transactions
200	5. C-code structure 5.1 Node structure
204	5.2 A node’s linc component
207	5.3 Other node components
210	6. Physical layers 6.1 Type 1 module
224	6.2 Type 18-DE-500 signals and power control
229	6.3 Type 18-DE-500 module extender cable
231	6.4 Type 18-DE-500 cable-link
234	6.5 Serial interconnection
246	7. Bibliography
247	Annex A (Informative) Ringlet initialization
249	Annex B (Informative) SCI design models