IEEE 1685-2009
$147.33
IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows
| Published By | Publication Date | Number of Pages |
| IEEE | 2009 |
New IEEE Standard – Superseded. Conformance checks for extensible Markup Language (XML) data designed to describe electronic systems are formulated by this standard. The meta-data forms that are standardized include: components, systems, bus interfaces and connections, abstractions of those buses, and details of the components including address maps, register and field descriptions, and file set descriptions for use in automating design, verification, documentation, and use flows for electronic systems. A set of XML schemas of the form described by the World Wide Web Consortium (W3CĀ®) and a set of semantic consistency rules (SCRs) are included. A generator interface that is portable across tool environments is provided. The specified combination of methodology-independent meta-data and the tool-independent mechanism for accessing that data provides for portability of design data, design methodologies, and environment implementations.
PDF Catalog
| PDF Pages | PDF Title |
|---|---|
| 1 | IEEE Std 1685-2009 Front cover |
| 3 | Title page |
| 4 | Acknowledgment Abstract/Keywords |
| 6 | Introduction |
| 7 | Notice to users Laws and regulations Copyrights Updating of IEEE documents Errata Interpretations Patents |
| 8 | Participants |
| 11 | Contents |
| 15 | Important notice 1. Overview 1.1 Scope |
| 16 | 1.2 Purpose 1.3 Design environment |
| 20 | 1.4 IP-XACT Enabled implementations |
| 21 | 1.5 Conventions used |
| 26 | 1.6 Use of color in this standard 1.7 Contents of this standard |
| 27 | 2. Normative references |
| 29 | 3. Definitions, acronyms, and abbreviations 3.1 Definitions |
| 35 | 3.2 Acronyms and abbreviations |
| 37 | 4. Interoperability use model 4.1 Roles and responsibilities |
| 38 | 4.2 IP-XACT IP exchange flows |
| 41 | 5. Interface definition descriptions 5.1 Definition descriptions 5.2 Bus definition |
| 44 | 5.3 Abstraction definition |
| 45 | 5.4 Ports |
| 46 | 5.5 Wire ports |
| 48 | 5.6 Qualifiers |
| 50 | 5.7 Wire port group |
| 52 | 5.8 Wire port mode constraints |
| 53 | 5.9 Wire port mirrored-mode constraints |
| 55 | 5.10 Transactional ports |
| 57 | 5.11 Transactional port group |
| 58 | 5.12 Extending bus and abstraction definitions |
| 61 | 5.13 Clock and reset handling |
| 63 | 6. Component descriptions 6.1 Component |
| 66 | 6.2 Interfaces 6.3 Interface interconnections |
| 68 | 6.4 Complex interface interconnections |
| 70 | 6.5 Bus interfaces |
| 81 | 6.6 Component channels |
| 83 | 6.7 Address spaces |
| 95 | 6.8 Memory maps |
| 111 | 6.9 Remapping |
| 116 | 6.10 Registers |
| 134 | 6.11 Models |
| 165 | 6.12 Component generators |
| 167 | 6.13 File sets |
| 179 | 6.14 Choices |
| 181 | 6.15 White box elements |
| 182 | 6.16 White box element reference |
| 184 | 6.17 CPUs |
| 185 | 7. Design descriptions 7.1 Design |
| 187 | 7.2 Design component instances |
| 189 | 7.3 Design interconnections |
| 190 | 7.4 Active, monitored, and monitor interfaces |
| 192 | 7.5 Design ad hoc connections |
| 194 | 7.6 Design hierarchical connections |
| 197 | 8. Abstractor descriptions 8.1 Abstractor |
| 199 | 8.2 Abstractor interfaces |
| 201 | 8.3 Abstractor models |
| 203 | 8.4 Abstractor views |
| 205 | 8.5 Abstractor ports |
| 207 | 8.6 Abstractor wire ports |
| 209 | 8.7 Abstractor generators |
| 213 | 9. Generator chain descriptions 9.1 generatorChain |
| 215 | 9.2 generatorChainSelector |
| 216 | 9.3 generatorChain component selector |
| 217 | 9.4 generatorChain generator |
| 221 | 10. Design configuration descriptions 10.1 Design configuration 10.2 designConfiguration |
| 223 | 10.3 generatorChainConfiguration |
| 225 | 10.4 interconnectionConfiguration |
| 227 | 11. Addressing and data visibility 11.1 Calculating the bit address of a bit in a memory map |
| 228 | 11.2 Calculating the bus address at the slave bus interface 11.3 Address modifications of an interconnection |
| 229 | 11.4 Address modifications of a channel |
| 230 | 11.5 Addressing in the master 11.6 Visibility of bits |
| 232 | 11.7 Address translation in a bridge |
| 233 | Annex A (informative) Bibliography |
| 235 | Annex B (normative) Semantic consistency rules |
| 259 | Annex C (normative) Common elements and concepts |
| 277 | Annex D (normative) Types |
| 281 | Annex E (normative) Dependency XPATH |
| 285 | Annex F (informative) External bus with an internal/digital interface |
| 287 | Annex G (normative) Tight generator interface |
| 365 | Annex H (informative) Bridges and channels |
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