IEEE P1800
$217.21
IEEE Draft Standard for SystemVerilog–Unified Hardware Design, Specification, and Verification Language
| Published By | Publication Date | Number of Pages |
| IEEE | N/A | 1354 |
Revision Standard – Active – Draft. The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing test benches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages.
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