{"id":111154,"date":"2024-10-18T16:06:44","date_gmt":"2024-10-18T16:06:44","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-1596-1992\/"},"modified":"2024-10-24T22:00:31","modified_gmt":"2024-10-24T22:00:31","slug":"ieee-1596-1992","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-1596-1992\/","title":{"rendered":"IEEE 1596 1992"},"content":{"rendered":"

New IEEE Standard – Active. The scalable coherent interface (SCI) provides computer-bus-like services but, instead of a bus, uses a collection of fast point-to-point unidirectional links to provide the far higher throughput needed for high-performance multiprocessor systems. SCI supports distributed, shared memory with optional cache coherence for tightly coupled systems, and message-passing for loosely coupled systems. Initial SCI links are defined at 1 Gbyte\/s (16-bit parallel) and 1 Gb\/s (serial). For applications requiring modular packaging, an interchangeable module is specified along with connector and power. The packets and protocols that implement transactions are defined and their formal specification is provided in the form of computer programs. In addition to the usual read-and-write transactions, SCI supports efficient multiprocessor lock transactions. The distributed cache-coherence protocols are efficient and can recover from an arbitrary number of transmission failures. SCI protocols ensure forward progress despite multiprocessor conflicts (no deadlocks or starvation).<\/p>\n

PDF Catalog<\/h4>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
1<\/td>\nTitle page <\/td>\n<\/tr>\n
2<\/td>\nCopyright Page <\/td>\n<\/tr>\n
5<\/td>\nIntroduction <\/td>\n<\/tr>\n
9<\/td>\nParticipants <\/td>\n<\/tr>\n
11<\/td>\nCONTENTS <\/td>\n<\/tr>\n
13<\/td>\n1. Introduction
1.1 Document structure <\/td>\n<\/tr>\n
14<\/td>\n1.2 SCI overview <\/td>\n<\/tr>\n
20<\/td>\n1.3 Interconnect topologies <\/td>\n<\/tr>\n
25<\/td>\n1.4 Transactions <\/td>\n<\/tr>\n
42<\/td>\n1.5 Cache coherence <\/td>\n<\/tr>\n
47<\/td>\n1.6 Reliability, availability, and support (RAS) <\/td>\n<\/tr>\n
51<\/td>\n2. References, glossary, and notation
2.1 References
2.2 Conformance levels <\/td>\n<\/tr>\n
52<\/td>\n2.3 Glossary <\/td>\n<\/tr>\n
57<\/td>\n2.4 Bit and byte ordering <\/td>\n<\/tr>\n
58<\/td>\n2.5 Numerical values <\/td>\n<\/tr>\n
59<\/td>\n2.6 C code
3. Logical protocols and formats
3.1 Packet formats
3.2 Send and echo packet formats <\/td>\n<\/tr>\n
77<\/td>\n3.3 Logical packet encodings <\/td>\n<\/tr>\n
80<\/td>\n3.4 Transaction types <\/td>\n<\/tr>\n
91<\/td>\n3.5 Elastic buffers <\/td>\n<\/tr>\n
93<\/td>\n3.6 Bandwidth allocation <\/td>\n<\/tr>\n
108<\/td>\n3.7 Queue allocation <\/td>\n<\/tr>\n
112<\/td>\n3.8 Transaction errors <\/td>\n<\/tr>\n
116<\/td>\n3.9 Transmission errors <\/td>\n<\/tr>\n
122<\/td>\n3.10 Address initialization <\/td>\n<\/tr>\n
133<\/td>\n3.11 Packet encoding <\/td>\n<\/tr>\n
136<\/td>\n3.12 SCI-specific control and status registers <\/td>\n<\/tr>\n
152<\/td>\n4. Cache-coherence protocols
4.1 Introduction <\/td>\n<\/tr>\n
156<\/td>\n4.2 Coherence update sequences <\/td>\n<\/tr>\n
163<\/td>\n4.3 Minimal-set coherence protocols <\/td>\n<\/tr>\n
169<\/td>\n4.4 Typical-set coherence protocols <\/td>\n<\/tr>\n
178<\/td>\n4.5 Full-set coherence protocols <\/td>\n<\/tr>\n
193<\/td>\n4.6 C-code naming conventions <\/td>\n<\/tr>\n
197<\/td>\n4.7 Coherent read and write transactions <\/td>\n<\/tr>\n
200<\/td>\n5. C-code structure
5.1 Node structure <\/td>\n<\/tr>\n
204<\/td>\n5.2 A node’s linc component <\/td>\n<\/tr>\n
207<\/td>\n5.3 Other node components <\/td>\n<\/tr>\n
210<\/td>\n6. Physical layers
6.1 Type 1 module <\/td>\n<\/tr>\n
224<\/td>\n6.2 Type 18-DE-500 signals and power control <\/td>\n<\/tr>\n
229<\/td>\n6.3 Type 18-DE-500 module extender cable <\/td>\n<\/tr>\n
231<\/td>\n6.4 Type 18-DE-500 cable-link <\/td>\n<\/tr>\n
234<\/td>\n6.5 Serial interconnection <\/td>\n<\/tr>\n
246<\/td>\n7. Bibliography <\/td>\n<\/tr>\n
247<\/td>\nAnnex A (Informative) Ringlet initialization <\/td>\n<\/tr>\n
249<\/td>\nAnnex B (Informative) SCI design models <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEEE Standard for Scalable Coherent Interface (SCI)<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n2001<\/td>\n255<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":111155,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-111154","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/111154","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/111155"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=111154"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=111154"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=111154"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}