{"id":233317,"date":"2024-10-19T15:12:22","date_gmt":"2024-10-19T15:12:22","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/bs-en-62215-32013\/"},"modified":"2024-10-25T09:41:41","modified_gmt":"2024-10-25T09:41:41","slug":"bs-en-62215-32013","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/bsi\/bs-en-62215-32013\/","title":{"rendered":"BS EN 62215-3:2013"},"content":{"rendered":"
IEC 62215-3:2013 specifies a method for measuring the immunity of an integrated circuit (IC) to standardized conducted electrical transient disturbances. The disturbances, not necessarily synchronized to the operation of the device under test (DUT), are applied to the IC pins via coupling networks. This method enables understanding and classification of interaction between conducted transient disturbances and performance degradation induced in ICs regardless of transients within or beyond the specified operating voltage range.<\/p>\n
PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
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6<\/td>\n | English CONTENTS <\/td>\n<\/tr>\n | ||||||
8<\/td>\n | 1 Scope 2 Normative references 3 Terms and definitions <\/td>\n<\/tr>\n | ||||||
10<\/td>\n | 4 General <\/td>\n<\/tr>\n | ||||||
11<\/td>\n | 5 Coupling networks 5.1 General on coupling networks 5.2 Supply injection network 5.2.1 Direct injection Figures Figure 1 \u2013 Typical pin injection test implementation <\/td>\n<\/tr>\n | ||||||
12<\/td>\n | 5.2.2 Capacitive coupling 5.3 Input injection Figure 2 \u2013 Supply pin direct injection test implementation Figure 3 \u2013 Supply pin capacitive injection test implementation <\/td>\n<\/tr>\n | ||||||
13<\/td>\n | 5.4 Output injection Figure 4 \u2013 Input pin injection test implementation <\/td>\n<\/tr>\n | ||||||
14<\/td>\n | 5.5 Simultaneous multiple pin injection 6 IC configuration and evaluation 6.1 IC configuration and operating modes Figure 5 \u2013 Output pin injection test implementation Figure 6 \u2013 Multiple pin injection test implementation <\/td>\n<\/tr>\n | ||||||
15<\/td>\n | 6.2 IC monitoring 6.3 IC performance classes <\/td>\n<\/tr>\n | ||||||
16<\/td>\n | 7 Test conditions 7.1 General 7.2 Ambient electromagnetic environment 7.3 Ambient temperature 7.4 IC supply voltage 8 Test equipment 8.1 General requirements for test equipment 8.2 Cables 8.3 Shielding 8.4 Transient generator 8.5 Power supply 8.6 Monitoring and stimulation equipment <\/td>\n<\/tr>\n | ||||||
17<\/td>\n | 8.7 Control unit 9 Test set up 9.1 General 9.2 EMC test board Figure 7 \u2013 Test set-up diagram <\/td>\n<\/tr>\n | ||||||
18<\/td>\n | Figure 8 \u2013 Example of the routing from the injection port to a pin of the DUT <\/td>\n<\/tr>\n | ||||||
19<\/td>\n | 10 Test procedure 10.1 Test plan 10.2 Test preparation 10.3 Characterization of coupled impulses 10.4 Impulse immunity measurement <\/td>\n<\/tr>\n | ||||||
20<\/td>\n | 10.5 Interpretation and comparison of results 10.6 Transient immunity acceptance level 11 Test report <\/td>\n<\/tr>\n | ||||||
21<\/td>\n | Annex A (informative) Test board recommendations Tables Table A.1 \u2013 Position of vias over the board <\/td>\n<\/tr>\n | ||||||
24<\/td>\n | Figure A.1 \u2013 Typical EMC test board topology <\/td>\n<\/tr>\n | ||||||
25<\/td>\n | Figure A.2 \u2013 Example of implementation of multiple injection structures <\/td>\n<\/tr>\n | ||||||
26<\/td>\n | Annex B (informative) Selection hints for coupling and decoupling network values <\/td>\n<\/tr>\n | ||||||
28<\/td>\n | Annex C (informative) Industrial and consumer applications Table C.1 \u2013 Definition of pin types <\/td>\n<\/tr>\n | ||||||
29<\/td>\n | Table C.2 \u2013 Test circuit values <\/td>\n<\/tr>\n | ||||||
30<\/td>\n | Table C.3 \u2013 Example of IC impulse test level (IEC\u00a061000-4-4) <\/td>\n<\/tr>\n | ||||||
31<\/td>\n | Annex D (informative) Vehicle applications Table D.1 \u2013 IC pin type definition <\/td>\n<\/tr>\n | ||||||
32<\/td>\n | Table D.2 \u2013 Transient test level 12\u00a0V (ISO\u00a07637-2) <\/td>\n<\/tr>\n | ||||||
33<\/td>\n | Table D.3 \u2013 Transient test level 24\u00a0V (ISO\u00a07637-2) <\/td>\n<\/tr>\n | ||||||
34<\/td>\n | Table D.4 \u2013 Example of transient test specification <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" Integrated circuits. Measurement of impulse immunity – Non-synchronous transient injection method<\/b><\/p>\n |