This part of IEC 62240, which is a technical report, provides information when using semiconductor devices in wider temperature ranges than those specified by the device manufacturer. The uprating solutions described herein are considered exceptions, when no reasonable alternatives are available; otherwise devices are utilized within the manufacturers\u2019 specifications.<\/p>\n
The terms \u201cuprating\u201d and \u201cthermal uprating\u201d are being used increasingly in avionics industry discussions and meetings, and clear definitions are included in Clause 3. They were coined as shorthand references to a special case of methods commonly used in selecting electronic components for circuit design.<\/p>\n
This document describes the methods and processes for implementing this special case of thermal uprating. All of the elements of these methods and processes employ existing, commonly used best engineering practices. No new or unique engineering knowledge is needed to follow these processes, only a rigorous application of the overall approach.<\/p>\n
Even though the device is used at wider temperatures, the wider temperatures usage will be limited to those that do not compromise applications performance and reliability, particularly for devices with narrow feature size geometries (for example, 90 nm and less). This document does not imply that applications use the device to function beyond the absolute maximum rating limits specified by the original device manufacturer and assumes that:<\/p>\n
device usage outside the original device manufacturers\u2019 specified temperature ranges is done only when no reasonable alternative approach is available and is performed with appropriate justification;<\/p>\n<\/li>\n
if it is necessary to use devices outside the original device manufacturers\u2019 specified temperature ranges, it is done with documented and controlled processes that assure integrity of the electronic equipment.<\/p>\n<\/li>\n<\/ul>\n
| PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
|---|---|---|---|---|---|---|---|
| 2<\/td>\n | undefined <\/td>\n<\/tr>\n | ||||||
| 4<\/td>\n | CONTENTS <\/td>\n<\/tr>\n | ||||||
| 7<\/td>\n | FOREWORD <\/td>\n<\/tr>\n | ||||||
| 9<\/td>\n | INTRODUCTION <\/td>\n<\/tr>\n | ||||||
| 10<\/td>\n | 1 Scope 2 Normative references 3 Terms, definitions and abbreviated terms 3.1 Terms and definitions <\/td>\n<\/tr>\n | ||||||
| 14<\/td>\n | 3.2 Abbreviated terms 4 Selection provisions 4.1 General <\/td>\n<\/tr>\n | ||||||
| 15<\/td>\n | Figures Figure 1 \u2013 Flow chart for semiconductor devices over wider temperature ranges <\/td>\n<\/tr>\n | ||||||
| 16<\/td>\n | 4.2 Device selection, usage and alternatives 4.2.1 General 4.2.2 Alternatives 4.2.3 Device technology <\/td>\n<\/tr>\n | ||||||
| 17<\/td>\n | 4.2.4 Compliance with the electronic component management plan 4.3 Device capability assessment 4.3.1 General 4.3.2 Device package and internal construction capability assessment 4.3.3 Risk assessment (assembly level) <\/td>\n<\/tr>\n | ||||||
| 18<\/td>\n | 4.3.4 Device uprating methods <\/td>\n<\/tr>\n | ||||||
| 19<\/td>\n | 4.3.5 Device reliability assurance <\/td>\n<\/tr>\n | ||||||
| 20<\/td>\n | 4.4 Device quality assurance (QA) over wider temperature ranges 4.4.1 Decision for the optimum QA method <\/td>\n<\/tr>\n | ||||||
| 21<\/td>\n | 4.4.2 Device level testing 4.4.3 Higher level assembly testing 4.5.1 General 4.5.2 Semiconductor device change monitoring <\/td>\n<\/tr>\n | ||||||
| 22<\/td>\n | 4.6 Final electronic equipment assurance 4.7 Documentation and identification 4.7.1 Documentation 4.7.2 Device identification 4.7.3 Customer notification <\/td>\n<\/tr>\n | ||||||
| 23<\/td>\n | Figure 2 \u2013 Report form for documenting device usage over wider temperature ranges <\/td>\n<\/tr>\n | ||||||
| 24<\/td>\n | Annexes Annex A (informative) Device parameter re-characterisation A.1 Glossary of symbols <\/td>\n<\/tr>\n | ||||||
| 25<\/td>\n | A.2 Rationale for parameter re-characterisation A.2.1 General A.2.2 Assessment for uprateability Figure A.1 \u2013 Parameter re-characterisation <\/td>\n<\/tr>\n | ||||||
| 26<\/td>\n | A.3 Capability assurance A.3.1 Description A.3.2 Parameter re-characterisation process <\/td>\n<\/tr>\n | ||||||
| 27<\/td>\n | Figure A.2 \u2013 Flow diagram of parameter re-characterisation capability assurance process <\/td>\n<\/tr>\n | ||||||
| 28<\/td>\n | Tables Table A.1 \u2013 Example of sample size calculation <\/td>\n<\/tr>\n | ||||||
| 30<\/td>\n | Figure A.3 \u2013 Margin in electrical parameter measurement based on the results of the sample test <\/td>\n<\/tr>\n | ||||||
| 31<\/td>\n | A.3.3 Application capability assessment Figure A.4 \u2013 Schematic diagram of parameter limit modifications Table A.2 \u2013 Parameter re-characterisation example: SN74ALS244 octal buffer\/driver <\/td>\n<\/tr>\n | ||||||
| 32<\/td>\n | A.4 Quality assurance A.5 Factors to be considered in parameter re-characterisation Figure A.5 \u2013 Parameter re-characterisation device quality assurance <\/td>\n<\/tr>\n | ||||||
| 33<\/td>\n | Figure A.6 \u2013 Schematic of outlier products that can invalidate sample testing <\/td>\n<\/tr>\n | ||||||
| 34<\/td>\n | A.6 Report form for documenting device parameter re-characterisation Figure A.7 \u2013 Example of intermediate peak of an electrical parameter: Voltage feedback input threshold change for Motorola MC34261 power factor controller, see [4] <\/td>\n<\/tr>\n | ||||||
| 35<\/td>\n | Figure A.8 \u2013 Report form for documenting device parameter re-characterisation <\/td>\n<\/tr>\n | ||||||
| 36<\/td>\n | Annex B (informative) Stress balancing B.1 General B.2 Glossary of symbols B.3 Stress balancing B.3.1 General <\/td>\n<\/tr>\n | ||||||
| 37<\/td>\n | B.3.2 Determine the ambient temperature extremes B.3.3 Determine parameter relationship to power dissipation B.3.4 Determine the dissipated power versus ambient temperature relationship <\/td>\n<\/tr>\n | ||||||
| 38<\/td>\n | Figure B.1 \u2013 Iso-TJ curve: Relationship between ambient temperature and dissipated power <\/td>\n<\/tr>\n | ||||||
| 39<\/td>\n | B.3.5 Assess applicability of the method B.3.6 Determine the new parameter values <\/td>\n<\/tr>\n | ||||||
| 40<\/td>\n | B.3.7 Conduct parametric and functional tests B.4 Application example B.4.1 General Figure B.2 \u2013 Graph of electrical parameters versus dissipated power <\/td>\n<\/tr>\n | ||||||
| 41<\/td>\n | B.4.2 Determine the ambient temperature extremes B.4.3 Select the parameters that can be derated <\/td>\n<\/tr>\n | ||||||
| 42<\/td>\n | B.4.4 Construct an Iso-TJ plot B.4.5 Determine whether or not the device can be uprated B.4.6 Determine the new parameter values Figure B.3 \u2013 Iso-TJ curve for the Fairchild MM74HC244 <\/td>\n<\/tr>\n | ||||||
| 43<\/td>\n | B.4.7 Conduct parametric and functional tests B.5 Other notes B.5.1 Margins B.5.2 Cautions and limitations Figure B.4 \u2013 Power versus frequency curve for the Fairchild MM74HC244 <\/td>\n<\/tr>\n | ||||||
| 44<\/td>\n | Figure B.5 \u2013 Flow chart for stress balancing <\/td>\n<\/tr>\n | ||||||
| 45<\/td>\n | Figure B.6 \u2013 Report form for documenting stress balancing <\/td>\n<\/tr>\n | ||||||
| 46<\/td>\n | Annex C (informative) Parameter conformance assessment C.1 General C.2 Test plan C.2.1 General C.2.2 Critical parameters C.2.3 Minimum allowable test margins <\/td>\n<\/tr>\n | ||||||
| 47<\/td>\n | C.2.4 Test options Figure C.1 \u2013 Relationship of temperature ratings, requirements and margins <\/td>\n<\/tr>\n | ||||||
| 49<\/td>\n | Figure C.2 \u2013 Typical fallout distribution versus Treq-max <\/td>\n<\/tr>\n | ||||||
| 50<\/td>\n | C.2.5 Quality assurance <\/td>\n<\/tr>\n | ||||||
| 51<\/td>\n | Figure C.3 \u2013 Parameter conformance assessment flow <\/td>\n<\/tr>\n | ||||||
| 52<\/td>\n | Figure C.4 \u2013 Report form for documenting parameter conformance testing <\/td>\n<\/tr>\n | ||||||
| 53<\/td>\n | Annex D (informative) Higher assembly level testing D.1 General D.2 Process D.2.1 General D.2.2 Analysis of assembly test definition D.2.3 Perform assembly test <\/td>\n<\/tr>\n | ||||||
| 54<\/td>\n | D.2.4 Document results D.2.5 Maintenance notification Figure D.1 \u2013 Flow chart of higher level assembly testing <\/td>\n<\/tr>\n | ||||||
| 55<\/td>\n | Figure D.2 \u2013 Report form for documenting higherlevel assembly test at temperature extremes <\/td>\n<\/tr>\n | ||||||
| 56<\/td>\n | Bibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" Process management for avionics. Electronic components capability in operation – Temperature uprating<\/b><\/p>\n |