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BS EN IEC 62386-101:2022:2023 Edition

BS EN IEC 62386-101:2022:2023 Edition

$198.66

Digital addressable lighting interface – General requirements. System components

Published By Publication Date Number of Pages
BSI 2023 70
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PDF Pages PDF Title
2 undefined
5 Annex ZA (normative)Normative references to international publicationswith their corresponding European publications
7 English
CONTENTS
12 FOREWORD
14 INTRODUCTION
Figures
Figure 1 – IEC 62386 graphical overview
15 1 Scope
2 Normative references
16 3 Terms and definitions
21 4 General
4.1 Purpose
4.2 Version number
4.3 System structure and architecture
Tables
Table 1 – System components
22 4.4 System information flow
4.5 Command types
Figure 2 – System structure example
Figure 3 – Communication between bus units (example)
23 4.6 Bus units
4.6.1 Transmitters and receivers in bus units
4.6.2 Control gear
4.6.3 Input device
Table 2 – Transmitters and receivers in bus units
24 4.6.4 Single-master application controller
4.6.5 Multi-master application controller
4.6.6 Sharing an interface
25 4.6.7 Power for operation
Figure 4 – Example of a shared interface
26 4.7 Bus power supply and load calculations
4.7.1 Current demand coverage
4.7.2 Maximum signal current compliance
4.7.3 Simplified system calculation
4.8 Wiring
4.8.1 Wiring structure
4.8.2 Wiring specification
27 4.9 Electrical safety requirements
4.9.1 General
4.9.2 Insulation
4.9.3 Electric strength
4.9.4 Limitation of the touch current from the device to the bus
28 4.10 Earthing of the bus
4.11 Power interruptions at bus units
4.11.1 Different levels of power interruptions
4.11.2 Short power interruptions of external power supply
Table 3 – Power-interruption timing of external power
Table 4 – Power-interruption timing of bus power
29 4.11.3 External power cycle
4.11.4 Short interruptions of bus power supply
4.11.5 Bus power down
4.11.6 System start-up timing
Table 5 – Short power interruptions
30 Figure 5 – Start-up timing example
Table 6 – Start-up timing
31 5 Electrical specification
5.1 General
5.2 Marking of the interface
5.3 Capacitors between the interface and earth
5.4 Signal voltage rating
Table 7 – System voltage levels
32 5.5 Signal current rating
5.6 Marking of bus powered bus unit
Table 8 – Receiver voltage levels
Table 9 – Transmitter voltage levels
Table 10 – Current rating
33 5.7 Signal rise time and fall time
Figure 6 – Maximum signal rise and fall time measurements
Table 11 – Signal rise and fall times
34 6 Bus power supply
6.1 General
6.2 Marking of the bus power supply terminals
6.3 Capacitors between the interface and earth
6.4 Voltage rating
Figure 7 – Minimum signal rise and fall time measurements
35 6.5 Current rating
6.5.1 General current rating
6.5.2 Single bus power supply current rating
6.5.3 Integrated bus power supply current rating
6.5.4 Dynamic behaviour of the bus power supply
Table 12 – Bus power supply output voltage
Table 13 – Bus power supply current rating
36 Figure 8 – Bus power supply current behaviour
Table 14 – Bus power supply dynamic behaviour
37 6.6 Bus power supply timing requirements
6.6.1 Short power supply interruptions
6.6.2 Short circuit behaviour
Figure 9 – Bus power supply voltage behaviour
Table 15 – Short circuit timing behaviour
38 7 Transmission protocol structure
7.1 General
7.2 Bit encoding
7.2.1 Start bit and data bit encoding
7.2.2 Stop condition encoding
7.3 Frame description
Figure 10 – Frame example
Figure 11 – Bi-phase encoded bits
39 7.4 Frame types
7.4.1 16-bit forward frame
7.4.2 24-bit forward frame
7.4.3 32-bit forward frame
7.4.4 Reserved forward frame
7.4.5 Backward frame
7.4.6 Proprietary forward frames
40 8 Timing
8.1 Single-master transmitter timing
8.1.1 Single-master transmitter bit timing
8.1.2 Single-master transmitter frame sequence timing
Figure 12 – Bit timing example
Figure 13 – Settling time illustration
Table 16 – Transmitter bit timing
41 8.2 Receiver timing
8.2.1 Receiver bit timing
Table 17 – Transmitter settling time values
42 8.2.2 Receiver bit timing violation
Figure 14 – Receiver timing decision example
Table 18 – Receiver timing starting at the beginning of a logical bit
Table 19 – Receiver timing starting at an edge inside of a logical bit
43 8.2.3 Receiver frame size violation
8.2.4 Receiver frame sequence timing
8.2.5 Reception of backward frames
Table 20 – Receiver settling time values
44 8.3 Multi-master transmitter timing
8.3.1 Multi-master transmitter bit timing
8.3.2 Multi-master transmitter frame sequence timing
Table 21 – Multi-master transmitter bit timing
45 9 Method of operation
9.1 Dealing with frames and commands
9.1.1 General
Table 22 – Multi-master transmitter settling time values
46 9.1.2 Frame received or rejected
9.1.3 Frame accepted or ignored
9.1.4 Command accepted or ignored
9.1.5 Command executed or discarded
Figure 15 – Dealing with frames and commands
47 9.2 Collision avoidance, collision detection and collision recovery
9.2.1 General
9.2.2 Collision avoidance
9.2.3 Collision detection
48 Table 23 – Checking a logical bit, starting at an edge at the beginning of the bit
Table 24 – Checking a logical bit, starting at an edge inside the bit
49 9.2.4 Collision recovery
Figure 16 – Collision detection timing decision example
Table 25 – Collision recovery timing
50 9.3 Transactions
9.4 Send-twice forward frames and send-twice commands
Figure 17 – Collision recovery example
51 9.5 Command iteration
9.6 Usage of a shared interface
9.6.1 General
Table 26 – Transmitter command iteration timing
Table 27 – Receiver command iteration timing
52 9.6.2 Backward frames
9.6.3 Forward frames
9.7 Use of multiple bus power supplies
10 Declaration of variables
11 Definition of commands
53 Annex A (informative) Background information for systems
A.1 Wiring information
54 A.2 System architectures
A.2.1 General
A.2.2 Single-master architecture
Table A.1 – Maximum cable length
55 A.2.3 Multi-master architecture with one application controller
Figure A.1 – Single-master architecture example
56 A.2.4 Multi-master architecture with more than one application controller
Figure A.2 – Multi-master architecture example with one application controller
57 A.2.5 Multi-master architecture with integrated input device
Figure A.3 – Multi-master architecture example with two application controllers
58 A.2.6 Multi-master architecture with integrated input device and power supply
Figure A.4 – Multi-master architecture example with integrated input device
59 A.3 Collision detection
Figure A.5 – Multi-master architecture example with integratedinput device and bus power supply
60 A.4 Timing definition explanations
A.4.1 General
A.4.2 Receiver timing
A.4.3 Transmitter timing
Figure A.6 – Collision detection timing diagram
61 A.4.4 Grey areas
A.5 Maximum current consumption calculation explanation
A.5.1 Single bus power supply
Figure A.7 – Transmitter and receiver timing illustration
62 A.5.2 Multiple bus power supplies
Figure A.8 – Bus power supply current values
Figure A.9 – Current demand coverage
63 A.5.3 Redundant bus power supplies
Figure A.10 – Combination of four bus power supplies
Figure A.11 – Redundant bus power supplies
64 A.6 Communication layer overview
A.6.1 General
Table A.2 – OSI layer model of the IEC 62386 series
65 A.6.2 Physical layer
A.6.3 Data link layer
A.6.4 Network layer
A.6.5 Transport layer
A.6.6 Session layer
A.6.7 Presentation layer
A.6.8 Application layer
A.7 Effects of combining version number 1 and version number 2.y devices
66 Table A.3 – Effects of combining version number 1 and version number 2.y devices
67 Annex B (informative) Touch current
Figure B.1 – Touch current from a bus unit
Figure B.2 – Summation of touch currents from several bus units
68 Bibliography

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