IEEE 2804-2019

$59.04

IEEE Standard for Software-Hardware Interface for Multi-Many-Core

Published By	Publication Date	Number of Pages
IEEE	2019

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Category: IEEE

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Description

New IEEE Standard – Active. This standard is intended primarily for tool developers and hardware developers who would use Software Hardware Interface for Multi-Many-core (SHIM) to exchange hardware description for software tools. It also attempts to provide software developers with insights into what hardware information is described in SHIM to foster understanding of the intention and the extent of SHIM.

PDF Catalog

PDF Pages	PDF Title
1	IEEE Std 2804-2019 Front Cover
2	Title page
4	Important Notices and Disclaimers Conerning IEEE Standards Documents
7	Participants
8	Introduction
9	Contents
11	1. Overview 1.1 Scope 1.2 Purpose 1.3 Word usage
12	1.4 General introduction 1.4.1 Interface
14	1.4.2 Software view—what is in and what is not
15	1.4.3 XML 1.4.3.1 Data binding 1.4.3.2 Who creates SHIM XML 1.4.4 SHIM Editor 1.4.5 Reference authoring tools
16	1.4.6 Changes introduced in SHIM 2.0
19	2. Normative references 3. Definitions 4. SHIM concepts 4.1 Topology—ComponentSet
20	4.2 Inter-core communication(CommunicationSet
21	4.3 Frequency and voltage(FrequencyVoltageSet
22	4.4 Communication network utilization and contention(ContentionGroupSet
23	4.5 Performance 4.5.1 General
24	4.5.2 Latency and pitch
25	4.5.3 Using triplets
27	4.6 Power—PowerConfiguration 4.7 Vendor extensions
28	4.8 Configuration 4.8.1 General 4.8.2 Common Configuration File (CCF)
30	5. Roadmap 5.1 General
31	5.2 Further componentization of SHIM XML 5.3 Hardware-related software properties 5.4 Schema refinement for smaller XML
32	6. SHIM interface 6.1 shim20.xsd
41	6.2 Conventions 6.3 Enumeration
43	6.4 Shim 6.5 SystemConfiguration
44	6.6 ComponentSet
45	6.6.1 MasterComponent
47	6.6.2 SlaveComponent 6.6.3 Cache
48	6.6.4 AccessTypeSet 6.6.5 AccessType
49	6.6.6 CommonInstructionSet
50	6.6.7 FunctionalUnitSet 6.6.8 FunctionalUnitSetFile 6.6.9 FunctionalUnit 6.6.10 Instruction
51	6.6.11 CustomInstruction
52	6.6.12 InstructionInput 6.6.13 InstructionOperation
53	6.6.14 InstructionOutput 6.6.15 Performance
54	6.6.16 Latency 6.6.17 Pitch 6.7 FrequencyVoltageSet
55	6.7.1 FrequencyDomain 6.7.2 VoltageDomain
56	6.7.3 OperatingPointSet 6.7.4 OperatingPoint
57	6.8 AddressSpaceSet 6.8.1 AddressSpace
58	6.8.2 SubSpace 6.8.3 MemoryConsistencyModel
59	6.8.4 MasterSlaveBindingSet 6.8.5 MasterSlaveBinding 6.8.6 Accessor
60	6.8.7 PerformanceSet 6.9 CommunicationSet 6.9.1 FIFOCommunication
61	6.9.2 SharedRegisterCommunication 6.9.3 InterruptCommunication
62	6.9.4 SharedMemoryCommunication
63	6.9.5 EventCommunication 6.9.6 ConnectionSet 6.9.7 Connection
64	6.10 ContentionGroupSet 6.10.1 ContentionGroup
65	6.10.2 Throughput 6.10.3 DataRate
66	6.11 PowerConfiguration 6.11.1 PowerConsumptionSet
67	6.11.2 PowerConsumption 6.12 VendorExtension
68	6.12.1 SystemConfigurationFile
69	6.12.2 PowerConfigurationFile 7. Use cases 7.1 Performance estimation: Auto-parallelizing compiler
70	7.1.1 Using CommonInstructionSet 7.1.2 Using PerformanceSet 7.1.3 Using Cache
71	7.1.4 Using FIFOCommunication 7.2 Tool configuration(RTOS configuration tool 7.2.1 Using ClockFrequency
72	7.2.2 Using SubSpace 7.3 Hardware modeling 8. SHIM XML authoring rules and guidelines
73	8.1 File name [rule]
74	8.2 The naming of various objects [rule] 8.3 Level of detail and precision [guideline] 9. Common Configuration File (CCF) 9.1 Concept 9.1.1 Multiple hardware configuration
75	9.1.2 Vendor-specific hardware features affecting SHIM objects 9.1.3 Configuration tool user interface
76	9.2 Interface 9.2.1 XML schema
78	9.2.2 Semantics 9.2.3 FormType 9.2.4 ConfigurationSet
79	9.2.5 Configuration 9.2.6 Item 9.2.7 Expression
80	9.2.8 Exp 9.2.9 Def 9.3 Examples 9.3.1 Generic
81	9.3.2 Nested configuration 10. FAQ
84	Back cover