New IEEE Standard – Inactive – Withdrawn. The Verilog(R) Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.

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PDF Pages	PDF Title
4	CONTENTS
21	Foreword
25	IEEE Introduction
27	1. Overview 1.1 Objectives of this standard 1.2 Conventions used in this standard
28	1.3 Syntactic description 1.4 Contents of this standard
30	1.5 Header file listings
31	1.6 Examples 1.7 Prerequisites
32	2. Lexical conventions 2.1 Lexical tokens 2.2 White space 2.3 Comments 2.4 Operators 2.5 Numbers
36	2.6 Strings
38	2.7 Identifiers, keywords, and system names
40	2.8 Attributes
46	3. Data types 3.1 Value set 3.2 Nets and variables
49	3.3 Vectors
50	3.4 Strengths
51	3.5 Implicit declarations 3.6 Net initialization 3.7 Net types
57	3.8 regs 3.9 Integers, reals, times, and realtimes
59	3.10 Arrays
60	3.11 Parameters
64	3.12 Name spaces
66	4. Expressions 4.1 Operators
78	4.2 Operands
83	4.3 Minimum, typical, and maximum delay expressions
85	4.4 Expression bit lengths
88	4.5 Signed expressions
90	5. Scheduling semantics 5.1 Execution of a model 5.2 Event simulation 5.3 The stratified event queue
91	5.4 The Verilog simulation reference model
92	5.5 Race conditions 5.6 Scheduling implication of assignments
95	6. Assignments 6.1 Continuous assignments
99	6.2 Procedural assignments
101	7. Gate and switch level modeling 7.1 Gate and switch declaration syntax
107	7.2 and, nand, nor, or, xor, and xnor gates
108	7.3 buf and not gates
109	7.4 bufif1, bufif0, notif1, and notif0 gates
110	7.5 MOS switches
112	7.6 Bidirectional pass switches 7.7 CMOS switches
113	7.8 pullup and pulldown sources
114	7.9 Logic strength modeling
115	7.10 Strengths and values of combined signals
128	7.11 Strength reduction by nonresistive devices 7.12 Strength reduction by resistive devices 7.13 Strengths of net types
129	7.14 Gate and net delays
133	8. User-defined primitives (UDPs) 8.1 UDP definition
137	8.2 Combinational UDPs
138	8.3 Level-sensitive sequential UDPs 8.4 Edge-sensitive sequential UDPs
139	8.5 Sequential UDP initialization
141	8.6 UDP instances
142	8.7 Mixing level-sensitive and edge-sensitive descriptions
143	8.8 Level-sensitive dominance
144	9. Behavioral modeling 9.1 Behavioral model overview
145	9.2 Procedural assignments
150	9.3 Procedural continuous assignments
153	9.4 Conditional statement
156	9.5 Case statement
160	9.6 Looping statements
162	9.7 Procedural timing controls
172	9.8 Block statements
175	9.9 Structured procedures
178	10. Tasks and functions 10.1 Distinctions between tasks and functions 10.2 Tasks and task enabling
183	10.3 Functions and function calling
189	11. Disabling of named blocks and tasks
192	12. Hierarchical structures 12.1 Modules
206	12.2 Overriding module parameter values
211	12.3 Ports
219	12.4 Hierarchical names
222	12.5 Upwards name referencing
224	12.6 Scope rules
226	13. Configuring the contents of a design 13.1 Introduction
227	13.2 Libraries
229	13.3 Configurations
233	13.4 Using libraries and configs
234	13.5 Configuration examples
236	13.6 Displaying library binding information 13.7 Library mapping examples
238	14. Specify blocks 14.1 Specify block declaration
239	14.2 Module path declarations
249	14.3 Assigning delays to module paths
253	14.4 Mixing module path delays and distributed delays
254	14.5 Driving wired logic
255	14.6 Detailed control of pulse filtering behavior
264	15. Timing checks 15.1 Overview
267	15.2 Timing checks using a stability window
275	15.3 Timing checks for clock and control signals
285	15.4 Edge-control specifiers
286	15.5 Notifiers: user-defined responses to timing violations
292	15.6 Enabling timing checks with conditioned events
293	15.7 Vector signals in timing checks
294	15.8 Negative timing checks
296	16. Backannotation using the Standard Delay Format (SDF) 16.1 The SDF annotator 16.2 Mapping of SDF constructs to Verilog
301	16.3 Multiple annotations
302	16.4 Multiple SDF files 16.5 Pulse limit annotation
303	16.6 SDF to Verilog delay value mapping
304	17. System tasks and functions 17.1 Display system tasks
313	17.2 File input-output system tasks and functions
324	17.3 Timescale system tasks
328	17.4 Simulation control system tasks
329	17.5 PLA modeling system tasks
333	17.6 Stochastic analysis tasks
335	17.7 Simulation time system functions
337	17.8 Conversion functions
338	17.9 Probabilistic distribution functions
347	17.10 Command line input
351	18. Value change dump (VCD) files 18.1 Creating the four state value change dump file
356	18.2 Format of the four state VCD file
366	18.3 Creating the extended value change dump file
370	18.4 Format of the extended VCD file
377	19. Compiler directives 19.1 `celldefine and `endcelldefine 19.2 `default_nettype
378	19.3 `define and `undef
380	19.4 `ifdef, `else, `elsif, `endif, `ifndef
384	19.5 `include 19.6 `resetall
385	19.7 `line 19.8 `timescale
387	19.9 `unconnected_drive and `nounconnected_drive
388	20. PLI overview 20.1 PLI purpose and history (informative) 20.2 User-defined system task or function names
389	20.3 User-defined system task or function types 20.4 Overriding built-in system task and function names 20.5 User-supplied PLI applications 20.6 PLI interface mechanism
390	20.7 User-defined system task and function arguments 20.8 PLI include files 20.9 PLI Memory Restrictions
391	21. PLI TF and ACC interface mechanism 21.1 User-supplied PLI applications
392	21.2 Associating PLI applications to a class and system task/function name
393	21.3 PLI application arguments
395	22. Using ACC routines 22.1 ACC routine definition 22.2 The handle data type
396	22.3 Using ACC routines 22.4 List of ACC routines by major category
402	22.5 Accessible objects
410	22.6 ACC routine types and fulltypes
413	22.7 Error handling
415	22.8 Reading and writing delay values
421	22.9 String handling
423	22.10 Using VCL ACC routines
430	23. ACC routine definitions
605	24. Using TF routines 24.1 TF routine definition 24.2 TF routine system task/function arguments 24.3 Reading and writing system task/function argument values
607	24.4 Value change detection 24.5 Simulation time 24.6 Simulation synchronization
608	24.7 Instances of user-defined tasks or functions 24.8 Module and scope instance names 24.9 Saving information from one system TF call to the next 24.10 Displaying output messages 24.11 Stopping and finishing
609	25. TF routine definitions
685	26. Using VPI routines 26.1 VPI system tasks and functions 26.2 The VPI interface
687	26.3 VPI object classifications
690	26.4 List of VPI routines by functional category
692	26.5 Key to data model diagrams
726	27. VPI routine definitions
787	Annex A (normative) Formal syntax definition
812	Annex B (normative) List of keywords
814	Annex C (informative) System tasks and functions
821	Annex D (informative) Compiler directives
823	Annex E (normative) acc_user.h
832	Annex F (normative) veriuser.h
840	Annex G (normative) vpi_user.h
854	Annex H (informative) Bibliography
855	Annex I (informative) List of Participants

Published By	Publication Date	Number of Pages
IEEE	2004	862


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Standard Title	IEC 61691-4 Ed.1 (IEEE Std 1364(TM)-2001): Behavioural Languages – Part 4: Verilog(C) Hardware Description Language
Published Code	IEEE
Publication Date	2004
Pages Count	862

IEEE IEC 61691 4 2004

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