{"id":194666,"date":"2024-10-19T12:21:09","date_gmt":"2024-10-19T12:21:09","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-1149-10-2017\/"},"modified":"2024-10-25T04:52:11","modified_gmt":"2024-10-25T04:52:11","slug":"ieee-1149-10-2017","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-1149-10-2017\/","title":{"rendered":"IEEE 1149.10 2017"},"content":{"rendered":"
New IEEE Standard – Active. Circuitry that may be built into an integrated circuit to assist in the test, maintenance, and support of assembled printed circuit boards, assembled multi-die packages, and the test of die internal circuits is defined in this standard. The circuitry includes a high-speed TAP (HSTAP) with a packet encoder\/decoder and distribution architecture through which instructions and test data are communicated. The standard leverages the languages of IEEE Std 1149.1\u2122 to describe and operate the on-chip circuits.<\/p>\n
PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
---|---|---|---|---|---|---|---|
1<\/td>\n | IEEE Std 1149.10\u2122-2017 Front Cover <\/td>\n<\/tr>\n | ||||||
2<\/td>\n | Title page <\/td>\n<\/tr>\n | ||||||
4<\/td>\n | Important Notices and Disclaimers Concerning IEEE Standards Documents <\/td>\n<\/tr>\n | ||||||
7<\/td>\n | Participants <\/td>\n<\/tr>\n | ||||||
8<\/td>\n | Introduction <\/td>\n<\/tr>\n | ||||||
9<\/td>\n | Contents <\/td>\n<\/tr>\n | ||||||
10<\/td>\n | List of Figures <\/td>\n<\/tr>\n | ||||||
11<\/td>\n | List of Tables <\/td>\n<\/tr>\n | ||||||
12<\/td>\n | 1. Overview 1.1 Scope 1.2 Need <\/td>\n<\/tr>\n | ||||||
13<\/td>\n | 1.3 Document outline 1.4 Specifications 1.5 Descriptions <\/td>\n<\/tr>\n | ||||||
14<\/td>\n | 1.6 Text conventions 1.7 Logic diagram conventions <\/td>\n<\/tr>\n | ||||||
15<\/td>\n | 2. Normative references 3. Definitions, abbreviations, acronyms, and special terms 3.1 Definitions <\/td>\n<\/tr>\n | ||||||
17<\/td>\n | 3.2 Abbreviations and acronyms <\/td>\n<\/tr>\n | ||||||
19<\/td>\n | 3.3 Numbers 4. High Speed Test Access Port 4.1 HSTAP <\/td>\n<\/tr>\n | ||||||
22<\/td>\n | 5. Packet encoder\/decoder and distribution architecture 5.1 PEDDA <\/td>\n<\/tr>\n | ||||||
28<\/td>\n | 6. Packet definitions 6.1 Packet overview <\/td>\n<\/tr>\n | ||||||
31<\/td>\n | 6.2 The CONFIG packet <\/td>\n<\/tr>\n | ||||||
33<\/td>\n | 6.3 The TARGET packet <\/td>\n<\/tr>\n | ||||||
34<\/td>\n | 6.4 The RESET packet <\/td>\n<\/tr>\n | ||||||
36<\/td>\n | 6.5 The RAW packet <\/td>\n<\/tr>\n | ||||||
37<\/td>\n | 6.6 The CH-SELECT packet <\/td>\n<\/tr>\n | ||||||
39<\/td>\n | 6.7 The SCAN packet <\/td>\n<\/tr>\n | ||||||
47<\/td>\n | 6.8 The BOND packet <\/td>\n<\/tr>\n | ||||||
48<\/td>\n | 6.9 The CONFIGR packet <\/td>\n<\/tr>\n | ||||||
49<\/td>\n | 6.10 The TARGETR packet <\/td>\n<\/tr>\n | ||||||
50<\/td>\n | 6.11 The RESETR packet <\/td>\n<\/tr>\n | ||||||
51<\/td>\n | 6.12 The RAWR packet <\/td>\n<\/tr>\n | ||||||
52<\/td>\n | 6.13 The CH-SELECTR packet <\/td>\n<\/tr>\n | ||||||
53<\/td>\n | 6.14 The SCANR packet <\/td>\n<\/tr>\n | ||||||
57<\/td>\n | 6.15 The BONDR packet <\/td>\n<\/tr>\n | ||||||
58<\/td>\n | 7. BSDL definitions 7.1 BSDL overview <\/td>\n<\/tr>\n | ||||||
60<\/td>\n | 7.2 Conformance attribute 7.3 HSTAP attribute <\/td>\n<\/tr>\n | ||||||
68<\/td>\n | 7.4 Packet_Map attribute <\/td>\n<\/tr>\n | ||||||
72<\/td>\n | 7.5 Control_Chars attribute <\/td>\n<\/tr>\n | ||||||
74<\/td>\n | 7.6 Scan_Channel_Association attribute <\/td>\n<\/tr>\n | ||||||
77<\/td>\n | 7.7 BSDL package for high speed JTAG <\/td>\n<\/tr>\n | ||||||
78<\/td>\n | 8. Channel bonding 8.1 Optimizing bandwidth <\/td>\n<\/tr>\n | ||||||
83<\/td>\n | 9. PDL 9.1 PDL Overview <\/td>\n<\/tr>\n | ||||||
84<\/td>\n | 9.2 iConfig command <\/td>\n<\/tr>\n | ||||||
85<\/td>\n | 9.3 iTarget command <\/td>\n<\/tr>\n | ||||||
86<\/td>\n | 9.4 iReset10 command <\/td>\n<\/tr>\n | ||||||
87<\/td>\n | 9.5 iRaw command <\/td>\n<\/tr>\n | ||||||
88<\/td>\n | 9.6 iBond command <\/td>\n<\/tr>\n | ||||||
89<\/td>\n | 9.7 Standardized PDL procedures <\/td>\n<\/tr>\n | ||||||
90<\/td>\n | 10. Compliance verification 10.1 Overview <\/td>\n<\/tr>\n | ||||||
95<\/td>\n | Annex A (informative) Bibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" IEEE Standard for High-Speed Test Access Port and On-Chip Distribution Architecture<\/b><\/p>\n |