In general, dynamic ON-resistance testing is a measure of charge trapping phenomena in GaN power transistors. This publication describes the guidelines for testing dynamic ON-resistance of GaN lateral power transistor solutions. The test methods can be applied to the following: a) GaN enhancement and depletion-mode discrete power devices [1] b) GaN integrated power solutions c) the above in wafer and package levels Wafer level tests are recommended to minimize parasitic effects when performing high precision measurements. For package level tests, the impact of package thermal characteristics should be considered so as to minimize any device under test (DUT) self-heating implications. The prescribed test methods may be used for device characterization, production testing, reliability evaluations and application assessments of GaN power conversion devices. This document is not intended to cover the underlying mechanisms of dynamic ON-resistance and its symbolic representation for product specifications.<\/p>\n
| PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
|---|---|---|---|---|---|---|---|
| 2<\/td>\n | undefined <\/td>\n<\/tr>\n | ||||||
| 4<\/td>\n | European foreword Endorsement notice <\/td>\n<\/tr>\n | ||||||
| 6<\/td>\n | English CONTENTS <\/td>\n<\/tr>\n | ||||||
| 7<\/td>\n | FOREWORD <\/td>\n<\/tr>\n | ||||||
| 9<\/td>\n | INTRODUCTION <\/td>\n<\/tr>\n | ||||||
| 10<\/td>\n | 1 Scope 2 Normative references 3 Terms, definitions, symbols and abbreviated terms 3.1 Terms and definitions 3.2 Symbols and abbreviated terms <\/td>\n<\/tr>\n | ||||||
| 11<\/td>\n | 4 Test circuits and waveforms 4.1 General 4.2 Inductive and resistive switching methods <\/td>\n<\/tr>\n | ||||||
| 12<\/td>\n | Figures Figure 1 \u2013 Inductive-resistive load \u201cdouble-pulse\u201d test circuit for hard-switching evaluation Figure 2 \u2013 Depiction of the hard-switching \u201cdouble-pulse\u201d test circuit (showing its similarity to a boost converter) <\/td>\n<\/tr>\n | ||||||
| 13<\/td>\n | Figure 3 \u2013 Simplified flowchart for inductive and\/or resistive switching based dynamic on-resistance test <\/td>\n<\/tr>\n | ||||||
| 14<\/td>\n | 4.3 Pulsed current-voltage (I-V) method Figure 4 \u2013 Representative continuous-pulse hard-switching waveforms for measuring dynamic on-resistance using the test circuits in Figure 1 and Figure 2 Figure 5 \u2013 Example test circuit for soft-switching on-resistance measurement(the gate and drain terminals are pulsed with independent voltage signals) <\/td>\n<\/tr>\n | ||||||
| 15<\/td>\n | Figure 6 \u2013 Simplified flowchart for soft switching based dynamic on-resistance test <\/td>\n<\/tr>\n | ||||||
| 16<\/td>\n | 5 Requirements Figure 7 \u2013 Illustrative timing diagram for measuring dynamic ON-resistance under OFF-state stress in soft-switching mode <\/td>\n<\/tr>\n | ||||||
| 18<\/td>\n | Bibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" Dynamic on-resistance test method guidelines for GaN HEMT based power conversion devices<\/b><\/p>\n |