{"id":79999,"date":"2024-10-17T18:39:56","date_gmt":"2024-10-17T18:39:56","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-1285-2006\/"},"modified":"2024-10-24T19:42:05","modified_gmt":"2024-10-24T19:42:05","slug":"ieee-1285-2006","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-1285-2006\/","title":{"rendered":"IEEE 1285 2006"},"content":{"rendered":"

New IEEE Standard – Active. This document specifies a scalable interface between mass-storage devices and controlling hard-ware\/software. The interface has been optimized for low-latency interconnects, assuming that the proces-sor\/controller and the storage device can often be co-located on the same printed-circuit board. The interface can also be used with longer-distance bus-like interconnects, including (but not limited to) IEEE Std 1394-1995 Serial Bus and IEEE Std 1596-1992 Scalable Coherent Interface.<\/p>\n

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PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
1<\/td>\nIEEE Standard for Scalable Storage Interface (S2I) <\/td>\n<\/tr>\n
3<\/td>\nTitle page <\/td>\n<\/tr>\n
5<\/td>\nIntroduction
Notice to users <\/td>\n<\/tr>\n
6<\/td>\nParticipants <\/td>\n<\/tr>\n
7<\/td>\nCONTENTS <\/td>\n<\/tr>\n
9<\/td>\n1. Overview
1.1 Scope
1.2 Purpose
1.3 Background <\/td>\n<\/tr>\n
10<\/td>\n1.4 Scalable storage interface properties
1.5 Historical perspective <\/td>\n<\/tr>\n
11<\/td>\n1.6 Non-storage applications <\/td>\n<\/tr>\n
12<\/td>\n1.7 S2I command execution
1.7.1 Shared command and status queues <\/td>\n<\/tr>\n
13<\/td>\n1.7.2 Command capabilities <\/td>\n<\/tr>\n
14<\/td>\n1.7.3 S2I capabilities
1.8 S2I topologies
1.8.1 Alpha-level interface <\/td>\n<\/tr>\n
15<\/td>\n1.8.2 Delta-level interfaces <\/td>\n<\/tr>\n
16<\/td>\n1.8.3 Multi-level RAID controllers <\/td>\n<\/tr>\n
17<\/td>\n1.9 S2I interconnects
1.9.1 Interconnect capabilities
1.10 Memory-mapped addresses <\/td>\n<\/tr>\n
18<\/td>\n1.11 Shared memory-mapped registers <\/td>\n<\/tr>\n
19<\/td>\n2. Normative references <\/td>\n<\/tr>\n
20<\/td>\n3. Glossary and notation
3.1 Definitions
3.1.1 Conformance levels
3.1.2 Definitions of S2I related terms <\/td>\n<\/tr>\n
23<\/td>\n3.2 Field names
3.3 C-code notation <\/td>\n<\/tr>\n
24<\/td>\n3.4 Bit and byte ordering
3.4.1 Endian ordering options <\/td>\n<\/tr>\n
25<\/td>\n3.4.2 Big-endian byte ordering <\/td>\n<\/tr>\n
26<\/td>\n3.4.3 Little-endian alternatives
3.5 Generic delta-level command lists
3.6 Data formats
3.6.1 Numerical values <\/td>\n<\/tr>\n
27<\/td>\n3.6.2 Reserved registers and fields <\/td>\n<\/tr>\n
28<\/td>\n4. Abbreviations and acronyms <\/td>\n<\/tr>\n
29<\/td>\n5. Alpha-level interface
5.1 Alpha-level overview
5.1.1 Alpha-level distinctions
5.1.2 Alpha-level components <\/td>\n<\/tr>\n
30<\/td>\n5.1.3 Alpha-level memory-mapped addresses
5.1.4 Buffer block access
5.2 Command execution <\/td>\n<\/tr>\n
31<\/td>\n5.2.1 Command-list additions
5.2.2 Out-of-order command execution
5.3 Alpha4 command and status entries
5.3.1 command entry format <\/td>\n<\/tr>\n
32<\/td>\n5.3.2 status-entry format <\/td>\n<\/tr>\n
33<\/td>\n5.4 Alpha8 command and status entries
5.4.1 Extended command entry format <\/td>\n<\/tr>\n
34<\/td>\n5.4.2 status-entry format
5.5 Command processing <\/td>\n<\/tr>\n
35<\/td>\n5.6 Alpha-level CSRs
5.6.1 Alpha-level CSR offset addresses
5.6.2 control register <\/td>\n<\/tr>\n
36<\/td>\n5.6.3 state register
5.6.4 Operational states <\/td>\n<\/tr>\n
38<\/td>\n6. Delta interface properties
6.1 Delta-level distinctions
6.2 Delta-level memory-mapped addresses <\/td>\n<\/tr>\n
39<\/td>\n6.2.1 Mover operations
6.2.2 Mover register addresses <\/td>\n<\/tr>\n
40<\/td>\n6.2.3 Device-buffer addressing
6.3 Address formats
6.3.1 Delta16\/Delta32 address formats <\/td>\n<\/tr>\n
41<\/td>\n6.3.2 Delta64 address formats
6.3.3 Address modes <\/td>\n<\/tr>\n
42<\/td>\n6.4 Command lists
6.4.1 Command list structure
6.4.2 Command prefetching
6.4.3 Command activation <\/td>\n<\/tr>\n
45<\/td>\n6.5 Legacy command-set support
6.6 Delta-level command processing
6.6.1 Delta-level command blocks <\/td>\n<\/tr>\n
47<\/td>\n6.6.2 Common delta-level command values <\/td>\n<\/tr>\n
48<\/td>\n6.6.3 Data transfer locations <\/td>\n<\/tr>\n
49<\/td>\n6.7 Command sequence ordering <\/td>\n<\/tr>\n
50<\/td>\n6.8 Input\/output transfers
6.8.1 Device space selections
6.8.2 Read\/write transfers <\/td>\n<\/tr>\n
51<\/td>\n6.9 Scatter\/gather transfers
6.9.1 Scattered system addresses
6.9.2 Scatter\/gather lists <\/td>\n<\/tr>\n
52<\/td>\n6.10 System-bus transactions
6.10.1 Read\/write transaction usage
6.10.2 Transaction requirements <\/td>\n<\/tr>\n
53<\/td>\n6.10.3 Transaction ordering
6.10.4 Idempotent transactions <\/td>\n<\/tr>\n
54<\/td>\n6.11 Status reports
6.11.1 Mailbox status reports <\/td>\n<\/tr>\n
55<\/td>\n6.11.2 Adjacent status reports
6.11.3 Status report writes <\/td>\n<\/tr>\n
56<\/td>\n6.11.4 Interrupt indications
6.12 Command synchronization <\/td>\n<\/tr>\n
57<\/td>\n6.12.1 Synchronized device-to-device transfers
6.12.2 Synchronized DMA transfers <\/td>\n<\/tr>\n
58<\/td>\n6.13 Error conditions
6.13.1 Fatal access errors
6.13.2 Cancelled commands <\/td>\n<\/tr>\n
59<\/td>\n6.14 Delta-level mover CSRs
6.14.1 CSR address offsets
6.14.2 wakeup register <\/td>\n<\/tr>\n
60<\/td>\n6.14.3 flags register
6.14.4 state register <\/td>\n<\/tr>\n
61<\/td>\n6.14.5 control register <\/td>\n<\/tr>\n
62<\/td>\n6.15 Operational mover states
6.15.1 Basic operational states
6.15.2 Optional operational states <\/td>\n<\/tr>\n
63<\/td>\n6.15.3 Flushing input buffers <\/td>\n<\/tr>\n
64<\/td>\n7. Delta interfaces
7.1 Delta16 overview
7.1.1 Delta16 distinctions
7.1.2 Command lists <\/td>\n<\/tr>\n
65<\/td>\n7.1.3 Delta16 command values <\/td>\n<\/tr>\n
66<\/td>\n7.1.4 Delta16 command entry formats <\/td>\n<\/tr>\n
73<\/td>\n7.1.5 Delta16 Mover CSRs <\/td>\n<\/tr>\n
75<\/td>\n7.2 Delta32 overview
7.2.1 Delta32 distinctions <\/td>\n<\/tr>\n
76<\/td>\n7.2.2 Delta32 command values <\/td>\n<\/tr>\n
77<\/td>\n7.2.3 Delta32 command entry formats <\/td>\n<\/tr>\n
83<\/td>\n7.3 Delta32 Mover CSRs
7.3.1 CSR address offsets <\/td>\n<\/tr>\n
84<\/td>\n7.4 Delta64 overview
7.4.1 Delta64 distinctions
7.4.2 Delta64 commands <\/td>\n<\/tr>\n
85<\/td>\n7.4.3 Delta64 command entry formats <\/td>\n<\/tr>\n
91<\/td>\n7.4.4 Delta64 CSR address offsets <\/td>\n<\/tr>\n
92<\/td>\n7.4.5 nextCommand register <\/td>\n<\/tr>\n
93<\/td>\nAnnex A (informative) Bibliography <\/td>\n<\/tr>\n
94<\/td>\nAnnex B (informative) Illustrative applications
B.1 Secure logins <\/td>\n<\/tr>\n
95<\/td>\nB.2 Scattered buffer allocation
B.2.1 Dynamic network-packet storage allocation
B.2.2 Saving sense (extended status) information <\/td>\n<\/tr>\n
96<\/td>\nB.3 Heartbeat timers
B.4 Event reports
B.5 Power-level management <\/td>\n<\/tr>\n
97<\/td>\nB.6 Timed command execution
B.6.1 Extended MoverCsr.state register
B.6.2 timeLimit register <\/td>\n<\/tr>\n
98<\/td>\nB.7 DiskLite architecture
B.7.1 Media space partitioning <\/td>\n<\/tr>\n
99<\/td>\nB.7.2 Supported features <\/td>\n<\/tr>\n
100<\/td>\nB.7.3 Information space addresses <\/td>\n<\/tr>\n
101<\/td>\nAnnex C (informative) Software based RAID
C.1 RAID I\/O driver software
C.2 Single-block OUTPUT <\/td>\n<\/tr>\n
103<\/td>\nC.3 Striped-block OUTPUT <\/td>\n<\/tr>\n
104<\/td>\nC.4 Erasure-correcting single-block INPUT <\/td>\n<\/tr>\n
105<\/td>\nC.5 Erasure-correcting multiple-block INPUT <\/td>\n<\/tr>\n
106<\/td>\nAnnex D (informative) Physical interface possibilities
D.1 Delta16-level backplane interface
D.1.1 Direct unit addressing <\/td>\n<\/tr>\n
107<\/td>\nD.1.2 Hardwired interrupts
D.2 Delta64 Serial Bus interface <\/td>\n<\/tr>\n
108<\/td>\nD.2.1 Serial Bus addressing
D.2.2 Delta64 addresses <\/td>\n<\/tr>\n
109<\/td>\nD.2.3 Dependent fields <\/td>\n<\/tr>\n
111<\/td>\nAnnex E (informative) C-code illustrations <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEEE Standard for Scalable Storage Interface<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n2006<\/td>\n136<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":80000,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-79999","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/79999","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/80000"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=79999"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=79999"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=79999"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}