{"id":81381,"date":"2024-10-17T18:54:10","date_gmt":"2024-10-17T18:54:10","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-iec-61691-4-2004\/"},"modified":"2024-10-24T19:46:34","modified_gmt":"2024-10-24T19:46:34","slug":"ieee-iec-61691-4-2004","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-iec-61691-4-2004\/","title":{"rendered":"IEEE IEC 61691 4 2004"},"content":{"rendered":"

New IEEE Standard – Inactive – Withdrawn. The Verilog(R) Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.<\/p>\n

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PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
4<\/td>\nCONTENTS <\/td>\n<\/tr>\n
21<\/td>\nForeword <\/td>\n<\/tr>\n
25<\/td>\nIEEE Introduction <\/td>\n<\/tr>\n
27<\/td>\n1. Overview
1.1 Objectives of this standard
1.2 Conventions used in this standard <\/td>\n<\/tr>\n
28<\/td>\n1.3 Syntactic description
1.4 Contents of this standard <\/td>\n<\/tr>\n
30<\/td>\n1.5 Header file listings <\/td>\n<\/tr>\n
31<\/td>\n1.6 Examples
1.7 Prerequisites <\/td>\n<\/tr>\n
32<\/td>\n2. Lexical conventions
2.1 Lexical tokens
2.2 White space
2.3 Comments
2.4 Operators
2.5 Numbers <\/td>\n<\/tr>\n
36<\/td>\n2.6 Strings <\/td>\n<\/tr>\n
38<\/td>\n2.7 Identifiers, keywords, and system names <\/td>\n<\/tr>\n
40<\/td>\n2.8 Attributes <\/td>\n<\/tr>\n
46<\/td>\n3. Data types
3.1 Value set
3.2 Nets and variables <\/td>\n<\/tr>\n
49<\/td>\n3.3 Vectors <\/td>\n<\/tr>\n
50<\/td>\n3.4 Strengths <\/td>\n<\/tr>\n
51<\/td>\n3.5 Implicit declarations
3.6 Net initialization
3.7 Net types <\/td>\n<\/tr>\n
57<\/td>\n3.8 regs
3.9 Integers, reals, times, and realtimes <\/td>\n<\/tr>\n
59<\/td>\n3.10 Arrays <\/td>\n<\/tr>\n
60<\/td>\n3.11 Parameters <\/td>\n<\/tr>\n
64<\/td>\n3.12 Name spaces <\/td>\n<\/tr>\n
66<\/td>\n4. Expressions
4.1 Operators <\/td>\n<\/tr>\n
78<\/td>\n4.2 Operands <\/td>\n<\/tr>\n
83<\/td>\n4.3 Minimum, typical, and maximum delay expressions <\/td>\n<\/tr>\n
85<\/td>\n4.4 Expression bit lengths <\/td>\n<\/tr>\n
88<\/td>\n4.5 Signed expressions <\/td>\n<\/tr>\n
90<\/td>\n5. Scheduling semantics
5.1 Execution of a model
5.2 Event simulation
5.3 The stratified event queue <\/td>\n<\/tr>\n
91<\/td>\n5.4 The Verilog simulation reference model <\/td>\n<\/tr>\n
92<\/td>\n5.5 Race conditions
5.6 Scheduling implication of assignments <\/td>\n<\/tr>\n
95<\/td>\n6. Assignments
6.1 Continuous assignments <\/td>\n<\/tr>\n
99<\/td>\n6.2 Procedural assignments <\/td>\n<\/tr>\n
101<\/td>\n7. Gate and switch level modeling
7.1 Gate and switch declaration syntax <\/td>\n<\/tr>\n
107<\/td>\n7.2 and, nand, nor, or, xor, and xnor gates <\/td>\n<\/tr>\n
108<\/td>\n7.3 buf and not gates <\/td>\n<\/tr>\n
109<\/td>\n7.4 bufif1, bufif0, notif1, and notif0 gates <\/td>\n<\/tr>\n
110<\/td>\n7.5 MOS switches <\/td>\n<\/tr>\n
112<\/td>\n7.6 Bidirectional pass switches
7.7 CMOS switches <\/td>\n<\/tr>\n
113<\/td>\n7.8 pullup and pulldown sources <\/td>\n<\/tr>\n
114<\/td>\n7.9 Logic strength modeling <\/td>\n<\/tr>\n
115<\/td>\n7.10 Strengths and values of combined signals <\/td>\n<\/tr>\n
128<\/td>\n7.11 Strength reduction by nonresistive devices
7.12 Strength reduction by resistive devices
7.13 Strengths of net types <\/td>\n<\/tr>\n
129<\/td>\n7.14 Gate and net delays <\/td>\n<\/tr>\n
133<\/td>\n8. User-defined primitives (UDPs)
8.1 UDP definition <\/td>\n<\/tr>\n
137<\/td>\n8.2 Combinational UDPs <\/td>\n<\/tr>\n
138<\/td>\n8.3 Level-sensitive sequential UDPs
8.4 Edge-sensitive sequential UDPs <\/td>\n<\/tr>\n
139<\/td>\n8.5 Sequential UDP initialization <\/td>\n<\/tr>\n
141<\/td>\n8.6 UDP instances <\/td>\n<\/tr>\n
142<\/td>\n8.7 Mixing level-sensitive and edge-sensitive descriptions <\/td>\n<\/tr>\n
143<\/td>\n8.8 Level-sensitive dominance <\/td>\n<\/tr>\n
144<\/td>\n9. Behavioral modeling
9.1 Behavioral model overview <\/td>\n<\/tr>\n
145<\/td>\n9.2 Procedural assignments <\/td>\n<\/tr>\n
150<\/td>\n9.3 Procedural continuous assignments <\/td>\n<\/tr>\n
153<\/td>\n9.4 Conditional statement <\/td>\n<\/tr>\n
156<\/td>\n9.5 Case statement <\/td>\n<\/tr>\n
160<\/td>\n9.6 Looping statements <\/td>\n<\/tr>\n
162<\/td>\n9.7 Procedural timing controls <\/td>\n<\/tr>\n
172<\/td>\n9.8 Block statements <\/td>\n<\/tr>\n
175<\/td>\n9.9 Structured procedures <\/td>\n<\/tr>\n
178<\/td>\n10. Tasks and functions
10.1 Distinctions between tasks and functions
10.2 Tasks and task enabling <\/td>\n<\/tr>\n
183<\/td>\n10.3 Functions and function calling <\/td>\n<\/tr>\n
189<\/td>\n11. Disabling of named blocks and tasks <\/td>\n<\/tr>\n
192<\/td>\n12. Hierarchical structures
12.1 Modules <\/td>\n<\/tr>\n
206<\/td>\n12.2 Overriding module parameter values <\/td>\n<\/tr>\n
211<\/td>\n12.3 Ports <\/td>\n<\/tr>\n
219<\/td>\n12.4 Hierarchical names <\/td>\n<\/tr>\n
222<\/td>\n12.5 Upwards name referencing <\/td>\n<\/tr>\n
224<\/td>\n12.6 Scope rules <\/td>\n<\/tr>\n
226<\/td>\n13. Configuring the contents of a design
13.1 Introduction <\/td>\n<\/tr>\n
227<\/td>\n13.2 Libraries <\/td>\n<\/tr>\n
229<\/td>\n13.3 Configurations <\/td>\n<\/tr>\n
233<\/td>\n13.4 Using libraries and configs <\/td>\n<\/tr>\n
234<\/td>\n13.5 Configuration examples <\/td>\n<\/tr>\n
236<\/td>\n13.6 Displaying library binding information
13.7 Library mapping examples <\/td>\n<\/tr>\n
238<\/td>\n14. Specify blocks
14.1 Specify block declaration <\/td>\n<\/tr>\n
239<\/td>\n14.2 Module path declarations <\/td>\n<\/tr>\n
249<\/td>\n14.3 Assigning delays to module paths <\/td>\n<\/tr>\n
253<\/td>\n14.4 Mixing module path delays and distributed delays <\/td>\n<\/tr>\n
254<\/td>\n14.5 Driving wired logic <\/td>\n<\/tr>\n
255<\/td>\n14.6 Detailed control of pulse filtering behavior <\/td>\n<\/tr>\n
264<\/td>\n15. Timing checks
15.1 Overview <\/td>\n<\/tr>\n
267<\/td>\n15.2 Timing checks using a stability window <\/td>\n<\/tr>\n
275<\/td>\n15.3 Timing checks for clock and control signals <\/td>\n<\/tr>\n
285<\/td>\n15.4 Edge-control specifiers <\/td>\n<\/tr>\n
286<\/td>\n15.5 Notifiers: user-defined responses to timing violations <\/td>\n<\/tr>\n
292<\/td>\n15.6 Enabling timing checks with conditioned events <\/td>\n<\/tr>\n
293<\/td>\n15.7 Vector signals in timing checks <\/td>\n<\/tr>\n
294<\/td>\n15.8 Negative timing checks <\/td>\n<\/tr>\n
296<\/td>\n16. Backannotation using the Standard Delay Format (SDF)
16.1 The SDF annotator
16.2 Mapping of SDF constructs to Verilog <\/td>\n<\/tr>\n
301<\/td>\n16.3 Multiple annotations <\/td>\n<\/tr>\n
302<\/td>\n16.4 Multiple SDF files
16.5 Pulse limit annotation <\/td>\n<\/tr>\n
303<\/td>\n16.6 SDF to Verilog delay value mapping <\/td>\n<\/tr>\n
304<\/td>\n17. System tasks and functions
17.1 Display system tasks <\/td>\n<\/tr>\n
313<\/td>\n17.2 File input-output system tasks and functions <\/td>\n<\/tr>\n
324<\/td>\n17.3 Timescale system tasks <\/td>\n<\/tr>\n
328<\/td>\n17.4 Simulation control system tasks <\/td>\n<\/tr>\n
329<\/td>\n17.5 PLA modeling system tasks <\/td>\n<\/tr>\n
333<\/td>\n17.6 Stochastic analysis tasks <\/td>\n<\/tr>\n
335<\/td>\n17.7 Simulation time system functions <\/td>\n<\/tr>\n
337<\/td>\n17.8 Conversion functions <\/td>\n<\/tr>\n
338<\/td>\n17.9 Probabilistic distribution functions <\/td>\n<\/tr>\n
347<\/td>\n17.10 Command line input <\/td>\n<\/tr>\n
351<\/td>\n18. Value change dump (VCD) files
18.1 Creating the four state value change dump file <\/td>\n<\/tr>\n
356<\/td>\n18.2 Format of the four state VCD file <\/td>\n<\/tr>\n
366<\/td>\n18.3 Creating the extended value change dump file <\/td>\n<\/tr>\n
370<\/td>\n18.4 Format of the extended VCD file <\/td>\n<\/tr>\n
377<\/td>\n19. Compiler directives
19.1 `celldefine and `endcelldefine
19.2 `default_nettype <\/td>\n<\/tr>\n
378<\/td>\n19.3 `define and `undef <\/td>\n<\/tr>\n
380<\/td>\n19.4 `ifdef, `else, `elsif, `endif, `ifndef <\/td>\n<\/tr>\n
384<\/td>\n19.5 `include
19.6 `resetall <\/td>\n<\/tr>\n
385<\/td>\n19.7 `line
19.8 `timescale <\/td>\n<\/tr>\n
387<\/td>\n19.9 `unconnected_drive and `nounconnected_drive <\/td>\n<\/tr>\n
388<\/td>\n20. PLI overview
20.1 PLI purpose and history (informative)
20.2 User-defined system task or function names <\/td>\n<\/tr>\n
389<\/td>\n20.3 User-defined system task or function types
20.4 Overriding built-in system task and function names
20.5 User-supplied PLI applications
20.6 PLI interface mechanism <\/td>\n<\/tr>\n
390<\/td>\n20.7 User-defined system task and function arguments
20.8 PLI include files
20.9 PLI Memory Restrictions <\/td>\n<\/tr>\n
391<\/td>\n21. PLI TF and ACC interface mechanism
21.1 User-supplied PLI applications <\/td>\n<\/tr>\n
392<\/td>\n21.2 Associating PLI applications to a class and system task\/function name <\/td>\n<\/tr>\n
393<\/td>\n21.3 PLI application arguments <\/td>\n<\/tr>\n
395<\/td>\n22. Using ACC routines
22.1 ACC routine definition
22.2 The handle data type <\/td>\n<\/tr>\n
396<\/td>\n22.3 Using ACC routines
22.4 List of ACC routines by major category <\/td>\n<\/tr>\n
402<\/td>\n22.5 Accessible objects <\/td>\n<\/tr>\n
410<\/td>\n22.6 ACC routine types and fulltypes <\/td>\n<\/tr>\n
413<\/td>\n22.7 Error handling <\/td>\n<\/tr>\n
415<\/td>\n22.8 Reading and writing delay values <\/td>\n<\/tr>\n
421<\/td>\n22.9 String handling <\/td>\n<\/tr>\n
423<\/td>\n22.10 Using VCL ACC routines <\/td>\n<\/tr>\n
430<\/td>\n23. ACC routine definitions <\/td>\n<\/tr>\n
605<\/td>\n24. Using TF routines
24.1 TF routine definition
24.2 TF routine system task\/function arguments
24.3 Reading and writing system task\/function argument values <\/td>\n<\/tr>\n
607<\/td>\n24.4 Value change detection
24.5 Simulation time
24.6 Simulation synchronization <\/td>\n<\/tr>\n
608<\/td>\n24.7 Instances of user-defined tasks or functions
24.8 Module and scope instance names
24.9 Saving information from one system TF call to the next
24.10 Displaying output messages
24.11 Stopping and finishing <\/td>\n<\/tr>\n
609<\/td>\n25. TF routine definitions <\/td>\n<\/tr>\n
685<\/td>\n26. Using VPI routines
26.1 VPI system tasks and functions
26.2 The VPI interface <\/td>\n<\/tr>\n
687<\/td>\n26.3 VPI object classifications <\/td>\n<\/tr>\n
690<\/td>\n26.4 List of VPI routines by functional category <\/td>\n<\/tr>\n
692<\/td>\n26.5 Key to data model diagrams <\/td>\n<\/tr>\n
726<\/td>\n27. VPI routine definitions <\/td>\n<\/tr>\n
787<\/td>\nAnnex A (normative) Formal syntax definition <\/td>\n<\/tr>\n
812<\/td>\nAnnex B (normative) List of keywords <\/td>\n<\/tr>\n
814<\/td>\nAnnex C (informative) System tasks and functions <\/td>\n<\/tr>\n
821<\/td>\nAnnex D (informative) Compiler directives <\/td>\n<\/tr>\n
823<\/td>\nAnnex E (normative) acc_user.h <\/td>\n<\/tr>\n
832<\/td>\nAnnex F (normative) veriuser.h <\/td>\n<\/tr>\n
840<\/td>\nAnnex G (normative) vpi_user.h <\/td>\n<\/tr>\n
854<\/td>\nAnnex H (informative) Bibliography <\/td>\n<\/tr>\n
855<\/td>\nAnnex I (informative) List of Participants <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEC 61691-4 Ed.1 (IEEE Std 1364(TM)-2001): Behavioural Languages – Part 4: Verilog(C) Hardware Description Language<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n2004<\/td>\n862<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":81382,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-81381","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/81381","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/81382"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=81381"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=81381"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=81381"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}